PS3 vs X360: Apples to Apples high level comparison...

Another assumption one can make if we don't want to believe nvidia extended their pixel pipeline design is they count the 2 (indipedent) co-issued Dot2 ops the first ALU can execute and they summed them with Dot4 from VS pipelines.
I don't even want to consider this option

 

That option would still make 2 full Dot4's/cycle because if they counted them all as just Dot products then how could we comparatively count the Dot Products coming from the Broadband Engine ?

 

We can't, it doesnt' make sense, that's why I refute this hypothesis.

 

http://www.extremetech.com/article2/0,1558,1817022,00.asp

Interview with one of the hardware guys on XBox 360.

On the memory bandwidth issue, it's my guess they're using Hypertransport again, ~22GB/sec keys in well with the current stats on the HT website, and IBM is part of the HT consortium. So that's one element that's a carryover it seems from the original box.

 

Where is everyone getting the Cell chip dot-product information from? i didn't think that the Cell had a dotproduct function? I'm confused.

 

SPEs and PPE's VMX unit haven't a dot product instruction AFAIK, but four vec4 dot products can be calculated at the same time with 4 fmadd instructions, so the average troughput it's one dot4 per clock cycle.
To be fair things are more complex than that as on SPEs fmadd instructions have a 6 cycles latency AFAIK..

 

So in other words it does have the equivalent of a dotproduct function... just with fairly high latency OK. Ok so then when you say average throughput is one dot4 per clock cycle are you talking per SPE or the entire chip?

 

A dot4 per cycle per SPE and even PPE's VMX unit should provide one dot4 per cycle.
PS3 CPU would peak at 8 dot4 per cycle.

 

He is talking about each SPE.

 

See this topic, this has probably already discuted but try a look.

http://www.psinext.com/forums/viewtopic.php?t=6988

 

PC999, as PSINext staff I might as well take point here and ask what it is exactly you want looked at? That's two pages of posts - some of them pretty long - and I think it would help if your question consisted of more than just 'take a look,' since there's two different conversations going on there.

 

Didn't DeanoC, ERP, or aaaaa00 say XeCPU has a special dot product instruction?

 

Just read my comments about the Xenon CPU patent I found some months ago
http://www.beyond3d.com/forum/viewtopic.php?p=437998&highlight=xenon+patent+interesting#437998

 

Cool thanks.

 

6cycles instruction latency in a 3+Ghz chip is actually Very low - not high.
For that matter I kinda expect PPE/XCPU instruction latencies to be higher then that.