Will it help with the size of the GPU/GPUs if it is a MP-configuration? IMHO no. So the comparison with the HD6470M (FLOPs, MPixel, die-area) is IMHO still valid.
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Will it help with the size of the GPU/GPUs if it is a MP-configuration? IMHO no. So the comparison with the HD6470M (FLOPs, MPixel, die-area) is IMHO still valid.
Of course will it help since the it'll automatically make performance scaling more flexible. If you look at ST Ericsson's device descriptions they mention smart-phones, tablets and others for the A9600 as well as for the A9500 f.e. I don't know what ST might be aiming for with the 9600 but it strikes me more as a high end tablet design for =/>2012 than anything else with some obscene resolution.
If you're comparing only sterile meaningless numbers than probably yes. However since there are still worlds apart between any kind of standalone and an embedded SoC GPU a comparison to a embedded GPU block and even better IP from IMG itself. As I said in order to match that GFLOP value you'd need a SGX543/4 MP16@400MHz or a SGX554 MP16@200MHz. For geometry and fill-rate ratings you'd obviously need less than that, but it still makes it hard for me to believe that the fore-mentioned Rogue GPU is one single chip.
Since each SGX543 is at 8mm2@65nm/200MHz a MP16@200MHz gets you to 128mm2@65nm; now add in the higher frequency above and quite a few more functionalities for S6, minus architectural improvements, scale down to 28nm and you might be close. It's really that "simple" *cough*
Since each SGX543 is at 8mm2@65nm/200MHz a MP16@200MHz gets you to 128mm2@65nm; now add in the higher frequency above and quite a few more functionalities for S6, minus architectural improvements, scale down to 28nm and you might be close. It's really that "simple" *cough*
Ich sollte wirklich nur in einem Forum posten.
So I will bite:
128mm² @ 65nm = 24mm² @ 28nm; with 3 times the MHz it would be again 8mm² (like SGX543 @ 65nm)
So if the performance is really for a single core (heaven forbid!) than a 16 core variant could be: 128mm² @ 600MHz = 3360 GFlops + 83,2 GPixel + TBDR advantage => ~~ HD5970
Sounds a "little" bit too good to be true.
Ich sollte wirklich nur in einem Forum posten.
So I will bite:
128mm² @ 65nm = 24mm² @ 28nm; with 3 times the MHz it would be again 8mm² (like SGX543 @ 65nm)
So if the performance is really for a single core (heaven forbid!) than a 16 core variant could be: 128mm² @ 600MHz = 3360 GFlops + 83,2 GPixel + TBDR advantage => ~~ HD5970
Sounds a "little" bit too good to be true.
Meaning that the MP theory now makes more sense or not? *kicher*
Simple then, for it to be single core,rogue needs to be natively x4 better than SGX554, and be clocked at 800Mhz in the ST chip.
Simple then, for it to be single core,rogue needs to be natively x4 better than SGX554, and be clocked at 800Mhz in the ST chip.
Doesn't help as we don't even know where that Rogue variant is placed within the family of S6 cores. When they started out with Series5 they had 510 (canned), 520 and 530 in their initial Series5 whitepaper. 530 saw first the light of day, 520 a lot later and they expanded later on to 535, 531, 540 up to the also canned 555. After that they decided to go MP; while MP comes with a portion of hw redundancy experience with it has also shown them that it's with that strategy way easier to scale performance and I don't see why they would abandon that idea even more so since ARM, Vivante and Qualcomm have also MP configs.
No that doesn't mean that that Rogue GPU should be MP at any price a MP, but I still find it hard to swallow that under 28nm you can cram out as much performance from a single IP core.
Does this make the ST-Ericsson Nova A9600 the most powerful SoC announced to sample in 2011, at least in the graphics department? OMAP5 will have at most a quad-core SGX544, Qualcomm's APQ8064 with a Adreno 320 GPU won't sample until 2012 and AFAIK Tegra4 won't sample until 2012 either. Unless Apple pulls a rabbit out of its hat (i.e. Cortex-A15+PowerVR 6 for 2012's 28nm A6) that IMHO makes ST-Ericsson king of the SoC graphics department for samples in 2011. But sadly that says nothing about availability in devices, of course.
I dont want to spoil the fun, but do people here even think that those "performance" numbers throwed around for marketing purpose have some real merit ? With the shity SOC bandwith and amount of memory could they even render something with a desktop level texture and geometry quality (especialy at those resolutions) ?
AMD and Nvidia will also reach 28nm and they dont reveal the cards 2 years before something even gets to market.
AMD and Nvidia will also reach 28nm and they dont reveal the cards 2 years before something even gets to market.
2 things...IMG don't often quote outlandish performance figures, sometimes their licencees do, but thats outside their control.
Your statement regards Nvidia is plain weird when today on the Tegra3 thread you've posted an Nvidia graph showing "imaginary" performance improvements level for various future platforms right out to 2014.
http://forum.beyond3d.com/showpost.php?p=1524924&postcount=16
Troll ?
Thats the same thing as here. They release marketing numbers and graphs that dont have anything common with reality.
Thats the same thing as here. They release marketing numbers and graphs that dont have anything common with reality.
No....you said amd and NVIDIA DIDN'T do it
"AMD and Nvidia will also reach 28nm and they dont reveal the cards 2 years before something even gets to market"
I don't remember how to calculate Gflops of single-core SGX 543. May I ask how to calculate it?
I only remember that each SGX543MP1 has 4 USSE2 (ALU), and each USSE2 only calculate 2 flops each cycle? Sorry if there is any mistaken information.
USSE2 is billed as having twice the peak floating point throughput as USSE, and that it can accomplish this through co-issuing.
According to various sources, particularly JohnH, USSE is capable of issuing per cycle:
4x 8/10bit fixed point MADD
2x FP16 floating point FMADD
1-2x FP32 floating point FMADD, allowing for 2x when one of the input operands is shared (data path limitation)
So if USSE2 can coissue FMADDs you can go ahead and double that. For some operations, particularly lowp working on pixels and suitable normals, you'll get a lot of throughput with the 10-bit MADDs, but technically those aren't actually even FLOPs. The 16-bit ones will probably be good for most fragment shading operations (see Mali-400, which only has FP16 capabilities, or Tegra 2 which is limited to FP20), while you'll want FP32 for vertex shading. 3D scenes tend to spend a lot more time in fragment shaders than vertex shaders so.. make of that what you will.
See Exophase's explanation above.
4 * MADDs (MUL + ADD = 2 FLOPs) per ALU * 4 ALUs/core = 32 FLOPs
16 cores * 32 FLOPs * 0.4GHz = 204.8 GFLOPs/s
http://www.imgtec.com/News/Release/index.asp?NewsID=412
Dated 24/11/2008 and the actual deal might have been closed even earlier than that. At that time (and it's not that much different with console deals) IHVs sell what they have available then and not what they'll have later on their road-map. No one is buying designs "on paper" these days.
