Our goal with the Cell is to be an order of magnitude faster

[McFly]

Maybe some nanotech cooling fins! 8)

But then where are the pins? On the other side of the chip?

Fredi

 

[nAo]

So someone familiar with dimensions of a dollar coin please whip up the die area figure, stat! 8)

That coin should have a 26.5 mm diameter. Coin area should be about 550 mm2

 

[j^aws]

Maybe some nanotech cooling fins! 8)

But then where are the pins? On the other side of the chip?

Fredi

I can't see pin shadows against that coin...

 

[rabidrabbit]

Cheers Happy! Can I ask where did you find these?

Some IBM employee at Gamesradar.com. He has some presentation and he posted these on the forums.

I've just had the full details drop in to me, also a few fancy slide shows that'll be screened to the press etc.

http://forum.gamesradar.com/viewforum.php?f=12

So there are... other places.... with creatures that live beyond our borders?
But we are told not stray into their place, and they do not come into ours.

 

[Fafalada]

That coin should have a 26.5 mm diameter. Coin area should be about 550 mm2

Ok, after looking at the picture, I can discern that the shorter side of the chip rectangle is exactly half the diameter (13.25mm), and longer is about 0.8399060% of the diameter (I have very sharp eyes), giving me 22.257508 mm.

...
...

OMG CELL has a die area of 294.912 mm2

 

[rabidrabbit]

Is that much or little :?

 

[nAo]

OMG CELL has a die area of 294.912 mm2

At least it will be funny to see how our super-accurate measures are off record once the real die area will be public

 

[V3]

OMG CELL has a die area of 294.912 mm2

I don't know my coin dimension, but I know my choc chips And I'll second that (Unless they have smaller chock chips over there)

Is that much or little

much

 

[gleemax]

My rough estimate was 235.3-253.3 mm².

I couldn't really take the angle of the picture into account. Plus, my math could be wrong.

 

[nAo]

I don't know my coin dimension, but I know my choc chips And I'll second that (Unless they have smaller chock chips over there)

Emh..cough...Have you actually measured your chock chips?

 

[gleemax]

If someone wants to make an estimate based on the chocolate chip picture, I think it would be better to use the teaspoon as a reference.

 

[Simon F]

I can't see pin shadows against that coin...

There are no pins on a chip. Instead there are pads to which gold wires are bonded. These in turn then go to the pins/balls of the package.

IIRC, the pads are usually located around the outside of the device.

 

[hey69]

cock chips? what the hell is that

 

[Simon F]

OMG CELL has a die area of 294.912 mm2

So equivalent to more than 17x17mm - that's a big one.

 

[Gubbi]

David Wang posted a few tidbits @ Real World Tech

Die size in 90um: 206mm^2

Probably power constrained.

Cheers
Gubbi

 

[V3]

Die size in 90um: 206mm^2

Guess I forgot my choc chip are supersize

Pretty much expected die size for 90nm Cell.

 

[V3]

David Wang wrote:

The CELL processor presented has 1 64b PPC core acting as the traditional scalar processor, complete with its own L2. The PPE (PowerPC processing Element) is connected to 8 other SPE's (Synergistic Processing Elements) The SPE's are the magic glue that is suppose to contain enormous amount of compute power and a bunch of them gets you the enormously large flop rating that we've all head much about.

Some stats.

1. 90nm SOI process.

2. Logic depth is functionally equivalent to about 20 FO4 (est), but circuit speed equivalence is 11 FO4 per stage. The short pipestage circuit depth is reached with "circuit efficiencies" and Dynamic logic !?!

3. With per stage delay of 11 FO4, the schmoo plots show that the SPE's can crank from 3.2 GHz @ 0.9V Vdd to 5.2 GHz @ 1.3 V Vdd. The entire chip has similar frequency/voltage range, but to get to 5.2 Ghz @ 1.3V, each SPE will eat 11~12W. Add in the rest and the chip will get really hot. 4 GHz @ 1.1V = 4W per SPE seems to be the nominal range.

4. Die size per SPE is 2.5 x 5.81 mm^2. The entire chip with 8 SPE's seems to be about 17.2 x 12 mm^2. That seems to be an awfully large chip for IBM. The CPU to be used in PS3/Xbox2 will probably be the 65nm version or it'll have to have fewer SPE's.

6. As previously announced, the off chip I/O interface is Rambus Redwood and the memory interface is XDR. Similar clocking/deskewing schemes. Looks to be about ~50 GB/s BW to memory, and 50~100 GB/s to I/O.

I'll write up articles as the papers are presented.

That's pretty niffty info

 

[Psikotiko]

The CPU to be used in PS3/Xbox2 will probably be the 65nm version or it'll have to have fewer SPE's.

Xbox2????

 

[Fafalada]

Ah well, my joke was shortlived...
I guess I also didn't pimp the 294 number enough in GFlops thread already

Anyway great info, thanks Gubbi.

 

[Gubbi]

Die size in 90um: 206mm^2

Guess I forgot my choc chip are supersize

Pretty much expected die size for 90nm Cell.

Seems most of the specs is spot on in regard to estimates: 1 PE with 8APUs (or SPEs if you like) @ 4GHz. The PPE is simple and dumb (scalar), but fast (4GHz).

Very good peak FP performance with 256GFLOPS (unless you're Deadmeat)

The entire thing is power constrained at 50-70W @ 4GHz, so not much hope for doubling up on PEs (even in 65 nm).

Cheers
Gubbi