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Niebotskick
Newcomer
Interesting. Unified Memory has been moved from Maxwell to Volta (Pascal) ?
Its both.
The Anandtech liveblog made mention of very wide bus widths for stacked memory, which is consistent with HBM or some variety of future WideIO than the narrower Hybrid Memory Cube bus.
I haven't seen mention of an interposer, however, which would be needed for the highest bus widths.
I haven't seen mention of an interposer, however, which would be needed for the highest bus widths.
I thought I heard him make reference to "sitting on a wafer"
So NVLink is going to require both compatible motherboards and CPU's? And since theres no chance AMD will support this its basically reliant on Intel doing so.
Anyone care to wager on how likely that is? Would they need to support this to be able to compete with IBM in the supercomputer market when being used in combination with NV GPU's? Or is it more likely Intel will use a competitve technology?
I find it hard to get excited about this until there's some hint that we might actually see it in desktop PC's, which so far I'm not seeing.
Anyone care to wager on how likely that is? Would they need to support this to be able to compete with IBM in the supercomputer market when being used in combination with NV GPU's? Or is it more likely Intel will use a competitve technology?
I find it hard to get excited about this until there's some hint that we might actually see it in desktop PC's, which so far I'm not seeing.
Blazkowicz
Legend
A low latency interconnect is absolutely vital for a supercomputing chip. (even PC users complain of the PCIe)
AMD has had Hypertransport since 2003, Intel has had QPI from 2009, next-gen Xeon Phi has QPI which is a similar move.
The most likely use of NVLink in early system is given by their latter block diagram. Up to four GPUs communicate between them, probably accessing each other's data in a NUMA fashion. But communication to what's called "CPU" is done through slow PCI express.
The candidate for a NVLink-enabled CPU would certainly be an ARMv8 SoC. ARM SoC are friendly to customization, revolve around an internal bus that is thus impossibly fast and where various accelerators and high speed interfaces plug in.. Best known example is maybe AMD Seattle, for now.
From GPU's viewpoint, the prize is accessing at the least the "system CPU's" 1 TB or so memory.
An ugly chipset could mash up between QPI and NVLink maybe, but that would increase latency and Intel would have to allow it.
AMD has had Hypertransport since 2003, Intel has had QPI from 2009, next-gen Xeon Phi has QPI which is a similar move.
The most likely use of NVLink in early system is given by their latter block diagram. Up to four GPUs communicate between them, probably accessing each other's data in a NUMA fashion. But communication to what's called "CPU" is done through slow PCI express.
The candidate for a NVLink-enabled CPU would certainly be an ARMv8 SoC. ARM SoC are friendly to customization, revolve around an internal bus that is thus impossibly fast and where various accelerators and high speed interfaces plug in.. Best known example is maybe AMD Seattle, for now.
From GPU's viewpoint, the prize is accessing at the least the "system CPU's" 1 TB or so memory.
An ugly chipset could mash up between QPI and NVLink maybe, but that would increase latency and Intel would have to allow it.
I wonder who NVIDIA is working with for the memory. Hynix too? HBM seems the only wide IO memory which will be ready soon (HMC is not wide IO memory).
PS. guess they might be doing it with eDRAM at IBM ... expensive, but hell that silicon interposer is probably a 1000$ all by itself.
PS. guess they might be doing it with eDRAM at IBM ... expensive, but hell that silicon interposer is probably a 1000$ all by itself.
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Blazkowicz
Legend
I guess last year's news was easily forgotten or looked over, by me at least.
http://www.forbes.com/sites/davealt...celerator-and-strategic-partnership-with-ibm/
From wikipedia's article on the POWER8 we even have a name for the bus. That's CAPI?
It says it is layered on top of PCIe 3.0 but that would suck. I would think the nvidia GPU (and presumably the POWER8 CPU) use the physical PCIe 3.0 lines but run a different protocol over them.
Else (likely), a POWER8 variant would be fabbed with a more appropriate bus (that still speaks "CAPI" on a high level but otherwise has the huge speed, low latency and compatibility with the NVLink GPU)
/edit : wikipedia's sources, I'll let you look for yourself about the CAPI bus (not sure I like how that name sounds)
http://www.pcworld.idg.com.au/article/524768/ibm_new_power8_doubles_performance_watson_chip/
http://wccftech.com/ibm-power8-processor-architecture-detailed/
http://www.forbes.com/sites/davealt...celerator-and-strategic-partnership-with-ibm/
From wikipedia's article on the POWER8 we even have a name for the bus. That's CAPI?
It says it is layered on top of PCIe 3.0 but that would suck. I would think the nvidia GPU (and presumably the POWER8 CPU) use the physical PCIe 3.0 lines but run a different protocol over them.
Else (likely), a POWER8 variant would be fabbed with a more appropriate bus (that still speaks "CAPI" on a high level but otherwise has the huge speed, low latency and compatibility with the NVLink GPU)
/edit : wikipedia's sources, I'll let you look for yourself about the CAPI bus (not sure I like how that name sounds)
http://www.pcworld.idg.com.au/article/524768/ibm_new_power8_doubles_performance_watson_chip/
http://wccftech.com/ibm-power8-processor-architecture-detailed/
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