What about a chip where half the L2s are turned off?... Still 256-bit...
Why is L2 so prone to failure that a SKU arises with one broken? Surely L2 should be easy to keep working. e.g. with Bulldozer, a 6-core processor has the full 8MB of cache.
I wonder if this is NVidia's strategy to keep people/AIBs from overclocking 970 so that it exceeds 980? Hobble an L2 arbitrarily (it isn't actually broken) and the chips will always be slower than 980...
L2 should be easy to keep working, i.e. any failure should be easy to compensate for thanks to redundancy, but I think L2 slices are tied to ROPs, which should be roughly as likely to fail as just about anything else.