NV40 specs? Not likely. ;-)

[McFly]

Here are the NV40 specs:
300-350 Million Transistors on 90-nm process
750-800 MHz Core
16MB Embedded DRAM (134M trans.)
1.4 GHz 256-512MB DDR-II Memory
8 Pixel Rendering Pipelines (4 texels each)
16 Vertex Shader Engines
204.8 GB/sec Bandwidth (eDRAM)
44.8 GB/sec Bandwidth (DDR-II)
25.6 GigaTexels per Second
3 Billion Vertices per Second
DirectX 10 (or extended 9.1)
Release H2 2004

http://www.quake.co.il/modules/news/article.php?storyid=117

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Sorry if it's already posted somewhere else, but my internet connection is very slow right now. No idea why.

What do you think? I'm 99% sure that the real specs will be much below this.

Fredi

 

[BoddoZerg]

Yes, and the Xbox2 will consume 1.8 jiggawatts of power, and require plutonium, or a lightning strike.

 

[breez]

And how is this related to consoles?

 

[McFly]

And how is this related to consoles?

Release H2 2004

So it will be the base of the X-Box2 chip, just with more shader engines.

But they can't be real anyway.

Fredi

 

[wordsmyth]

Yes, and the Xbox2 will consume 1.8 jiggawatts of power, and require plutonium, or a lightning strike.

Actually, I believe its 1.21 jiggawatts powered by plutonium and run through a flux capacitor.

 

[Tagrineth]

Here are the NV40 specs:
300-350 Million Transistors on 90-nm process
750-800 MHz Core
16MB Embedded DRAM (134M trans.)
1.4 GHz 256-512MB DDR-II Memory
8 Pixel Rendering Pipelines (4 texels each)
16 Vertex Shader Engines
204.8 GB/sec Bandwidth (eDRAM)
44.8 GB/sec Bandwidth (DDR-II)
25.6 GigaTexels per Second
3 Billion Vertices per Second
DirectX 10 (or extended 9.1)
Release H2 2004

Well let's see...

At 130nm, the 125M transistor NV30 required a massive over-excessive cooler to run at 500MHz. So a 350Mtr chip on 90nm at 800MHz?! Hell no. And a 16MB cache would be highly resistant to being clocked that high.

Also 8 pipelines + 4 texels each? USELESS. The (f)utility of multiple TMU's per pipeline has already been discussed; 16x1 is way more likely, and even that is kinda iffy.

And finally, 16 vertex shader engine? nVidia stopped using "Vertex shaders", they have a floating-point processor array.

 

[Glonk]

Well let's see...

At 130nm, the 125M transistor NV30 required a massive over-excessive cooler to run at 500MHz. So a 350Mtr chip on 90nm at 800MHz?! Hell no. And a 16MB cache would be highly resistant to being clocked that high.

Actually I don't think 800MHz would be far off the mark for NV40.

NV30 is the "first gen" chip for a new architecture and was TSMC's first big-complex-chip on 0.13. It doesn't even have low-k working.

Once the process is refined and the chip tweaked, I'm thinking a NV30 @500MHz without the massive cooler would definitely be possible. Especially if they ever add low-k to it.

And then a 0.09 process with low-k + tweaked core, 800MHz isn't unreasonable for 2H04...

 

[Tagrineth]

Glonk... at 350 million transistors?

And with embedded RAM?

Embedded RAM is very resistant to high clock speeds. Especially that much of it...

 

[BoddoZerg]

Wasn't this rumor posted a -long- time ago?

Anyways, the mere "NV40 = 2H2004" thing disproves itself. If NV40 was delayed THAT long, nVidia would go the way of 3dfx for sure.

 

[PC-Engine]

Glonk... at 350 million transistors?

And with embedded RAM?

Embedded RAM is very resistant to high clock speeds. Especially that much of it...

The eDRAM can just be used as cache. It doesn't have to operate at the same speed as the core? For example like L2 cache on some CPUs?

 

[Vince]

At 130nm, the 125M transistor NV30 required a massive over-excessive cooler to run at 500MHz. So a 350Mtr chip on 90nm at 800MHz?! Hell no

Actually, I think this is likely. Remember that nVidia got burned by TSMC severly in that not only was 130nm process late, but their Low-K dielectrics had to be dropped from the current Nv30 iternation.

I wouldn't doubt a nvidia chip @ 1Ghz within 2/2.5 years if TSMC delivers.

Also 8 pipelines + 4 texels each? USELESS. The (f)utility of multiple TMU's per pipeline has already been discussed; 16x1 is way more likely, and even that is kinda iffy.

While you're right over all about the "f(utility)" [good wording] of conventional TCU's - I question just how this is going to work. I'd like to see the rescindment of any "fixed" pipelines and instead turn to virtual pipelines that are run over an array of processing elements and synthetically created and balanced autonomously (ideally threw on-board preformance/stress anaylizers) or thew Driver level control as in the P10.

nVidia stopped using "Vertex shaders", they have a floating-point processor array.

Agreed. Hopefully this idea will migrate to the rest of the chip as their is no need for discrete "P/FShaders" and "VShaders", but rather ambiguous elements.

 

[clem64]

Also 8 pipelines + 4 texels each? USELESS. The (f)utility of multiple TMU's per pipeline has already been discussed; 16x1 is way more likely, and even that is kinda iffy.

How is having multiple TMUs on the same pipeline useless?

What would be the advantages and disadvantages of, say, 8x1 VS. 4x2 ? (only in regards to T&L of course)

 

[Tagrineth]

clem64: If you're doing anything procedural or using proper pixel shaders, the additional TMU's go idle.

 

[megadrive0088]

Yes its obvious these specs are completely fabricated .