noob question

[Ante P]

Ok so I'm feeling stupid here.
How do I calculate AA fillrate as seen in some specifications?

I've tried "reverse engineering" by dividing by clock frequencies, pipelines, max suppoerted AA samples, max supported AA samples in a single cycle etc. and even memory speed but I still simply can't figure it out.

Or are they perhaps wieghing in HSR/Compression into the numbers and that's why it doesn't add up for me?

In any case help needed.

oh yeah the figure I want is AA samples/sec of course.

 

[Joe DeFuria]

It depends on the architecture...but all you should need is the number of pixel ppiplines, clock rate, and number of aa samples per pipeline per clock.

for R350: (*cough* edit* cough* )

380 Mhz
8 pipelines
2 AA samples per pipeline (per clock)

...380*8*2 = 6080 MegaSamples/sec (6.1 GigaSamples/sec)

 

[AlphaWolf]

That'd be r350 Joe.

R360 is 412mhz.

 

[tEd]

380*8*2

 

[Joe DeFuria]

380*8*2

Grrrrr.

 

[Ante P]

It depends on the architecture...but all you should need is the number of pixel ppiplines, clock rate, and number of aa samples per pipeline per clock.

for R350: (*cough* edit* cough* )

380 Mhz
8 pipelines
2 AA samples per pipeline (per clock)

...380*8*2 = 6080 MegaSamples/sec (6.1 GigaSamples/sec)

ahh now I see
I just noticed in Atis whitepapers they do it like this:

475 MHz * 12 pipes * 6 samples = 34.2 billion AA sampels/sec

for the 9800 Pro they (like the X800) claim 18.2 billion AA samples sec

so which one is correct
in my (rather tiny) brain the number of samples per clock seems the most logical

can anyone clarify?

oh yeah just checked out some GF4Ti specs and they also calculated by 4x MSAA, not 2 like they do in a single cycle

 

[Dave Baumann]

Ahhhhh, marketing.

All multisample chips only produce two samples per pipeline (regardless of what any marketting specs may say), so if the level of AA is greater than the number of samples it just spends more cycles doing it.

 

[Joe DeFuria]

AnteP...

Do you have a link to the whitepaper?

ATI's R3xx and R4xx architectures can perform 2 AA samples per pipe per clock. They loop-back to get 4 and 6 samples.

So the X800Pro would do 34.2 billion samples per pass, but 11.4 per second as a theoretical limit AFAIK.

 

[DemoCoder]

Wasn't the Xbox different, with 4 samples per clock? Atleast, that's what Abrash claimed. No idea if it's true.

 

[Dave Baumann]

NVIDIA had always maintained that NV2x was 4 samples per clock - I think the editors day was the first time I'd got David Kirk to say any different!

However, look at it logically, its all based on bandwidth - there just isn't much point going beyond 2 samples.

 

[Ante P]

Ahhhhh, marketing.

All multisample chips only produce two samples per pipeline (regardless of what any marketting specs may say), so if the level of AA is greater than the number of samples it just spends more cycles doing it.

So then , correct me if I'm being an a-hole , I assume that the figures presented by ATi and nVidia are faulty?

If they need an additional clockcycle for each 2x samples then we should divide the oh so great marketing numbers by 3 for ATi and 2 for nVidia?

...need sleep

 

[Maverick]

What if it's doing AA colour-compresion? If all the samples are the same, it should be able to produce all the samples in a single clock, at no cost to bandwidth, right?

 

[Xmas]

What if it's doing AA colour-compresion? If all the samples are the same, it should be able to produce all the samples in a single clock, at no cost to bandwidth, right?

Regarding bandwidth, yes. But the cases where you can really output one pixel per clock per pipe are pretty rare, so unless you go to 8xMSAA and beyond, the ROPs are rarely a bottleneck. There's not much to gain by more than two samples per pipe per clock.