Three DVI-I outputs per chassis in the quad-chip configuration for cost-effective three-channel, low-end image generator applications
with 2-to-24-sample full-scene antialiasing at screen resolutions up to 2048x1536 and fill rates up to 9.6Gpix/sec
sireric said:It's actually in its own box. Not too big though.
Very nice.
sireric said:It's actually in its own box. Not too big though.
Very nice.
sireric said:Though this E&S product is pretty sweet. Nearly 10GPixels/second fill rate is nice (4 chips in this design). Very nice. Actually, this might be a first on earth, no? IR3 couldn't do this, and I can't remember the pixel planes' fill rate.
Tagrineth said:Quantum3D did do a 32-chip VSA-100 which DID run at 10Gp/s.
AND the 16+ chip AAlchemy driver actually supports 16x 3dfx jittered scattered (er... I think that's what it's called... where there is one sample per row and column)-grid AA.
SO you can link together multiple of these beasts for even more power.....Multiple chassis solutions via dual-link DVI inputs and outputs for ultra-high-end applications
sireric said:No, each chip has a dedicated 20GB/sec bw bus. So, total is 80 GB/s of BW. The screen is divided into tiles, and each chip gets some of those tiles ("supertile" quote).
That effectively gives you the 9.x GPixel/s fillrate. Since each chip is capable of doing early rejection of triangles outside their tiles, the effective early culling performance is actually 64 pixels per clock per chip, or a total of 64*4*325 = 83.2 GPixels/sec.
sireric said:No, each chip has a dedicated 20GB/sec bw bus. So, total is 80 GB/s of BW. The screen is divided into tiles, and each chip gets some of those tiles ("supertile" quote).
That effectively gives you the 9.x GPixel/s fillrate. Since each chip is capable of doing early rejection of triangles outside their tiles, the effective early culling performance is actually 64 pixels per clock per chip, or a total of 64*4*325 = 83.2 GPixels/sec.
The link said:Exceptional fill rates enabled by a 256-bit wide unified memory interface and integrated multi-chip supertiling