Are going to be that ambitious with Valhalla? They're not really needing simplification in that sector yet unless a 360 chassis design is incoming (chance for MS to ditch steel and go with plastique!
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I *really* doubt it would be a 1-die chip. It could be 2 dies on 1 package aka an MCM (EDRAM now + GPU, and CPU), but 1 die alone would be counterintuitive and hassleful and in the end wouldn't help much compared to a multi chip module.
Anyway Valhalla's rumored specs don't make that much sense too- There has been no news on Xenon transitioning from the previous Chartered Semiconductor SOI process to a traditional bulk process that TSMC uses.
What I could see however, is MS switching from Chartered (which AFAIK is transitioning to 45 slowly) to GlobalFoundries Fab 1's 45nm SOI.
A Chartered -> GF dumb shrink would perhaps incur much less hassle than a SOI to bulk transition, and given that Chartered's 65nm silicon characteristics were like AMD's 65nm tech, which I have to say was quite bad relatively once clocks and voltage scaled up, the 45nm jump could actually bring a really nice reduction in terms of power consumption. 20W load reduction wouldn't be unreasonable.
On the GPU side, TMSC has just resolved its bigger issues with 40nm. Talk about timing.
TSMC's 40nm should help Xenos in terms of die area and density, so GPU and eDRAM could be combined into one. Power should go down to an extent, as Xenos is on the lower end of the clock curve and probably won't push leakage (if rampant) on the process to an inconvenient stage.
MS might take a few months more to wait it out, and to clear inventory of Falcon/Zephyr that really needs to be gone, then start getting Valhalla rolled out.