Make educated guess of DurangOrbis die sizes, tdps, and costs based on VGLeaks
- Thread starter Proelite
- Start date
Using the Sandy-E 15MB L3 as a base, doing some MS Paint measuring, and assuming perfect scaling over to a generic 28nm, the 32MB of SRAM in the rumoured Xbox 3 would take up around 200 mm^2 of die.
In the same space you could put almost 256MB of edram.
Either the SRAM is really worth it or Xbox has a relatively tiny amount of edram. How much would 32 MB of edram take up as a daughter die on whatever process the 360 S uses?
Huh. That's almost the size of the GPU.
I wonder why Microsoft is calling it Esram then, assuming VGLeaks didn't make a mistake reading their source materials.
bitsandbytes
Newcomer
Yeah that sounds massive. But it would explain the rumours of the SoC being very big.
Yeah, they could have gone with 64mb of Edram + extra 6 CUs, but that would run hotter?
I wouldn't draw any conclusions from the Sandy Bridge L3. For one, the clocks are much faster than what they are on the Durango CPU. You're looking at a 3.5 GHz versus 800 MHz part. The transistor density on the Durango will be a lot denser due to the lower clocks as well. Two, since it's a cache it has a lot more logic than a simple memory would have. Three, the fact that it's an L3 that needs to feed 6 cores is significant. It's probably a many-multiported design. Multiporting a memory has a huge impact on area. As much as doubling or tripling it.
But, if you really wanted to use a cache as a comparison, you're better looking at something like a Bobcat die since it's a similar manufacturer and similar design philosophy:
http://www.chip-architect.com/news/ontario_vs_atom.jpg
At 40nm, these L2's are 0.5 MB/3.4mm, 32MB would be around 220mm. With perfect scaling to 28nm, we're still looking at 110mm, but for a cache.
My feeling is that it's still not out of the question that it's an SRAM, it's probably only a 2 port design (1 read/1 write), but it should be below 100mm on a 28nm process, probably closer to 75mm.
But, if you really wanted to use a cache as a comparison, you're better looking at something like a Bobcat die since it's a similar manufacturer and similar design philosophy:
http://www.chip-architect.com/news/ontario_vs_atom.jpg
At 40nm, these L2's are 0.5 MB/3.4mm, 32MB would be around 220mm. With perfect scaling to 28nm, we're still looking at 110mm, but for a cache.
My feeling is that it's still not out of the question that it's an SRAM, it's probably only a 2 port design (1 read/1 write), but it should be below 100mm on a 28nm process, probably closer to 75mm.
It's worth noting that Intel's SRAM is pretty much the best and smallest in the business, AMD cache is probably going to take up more space per cell, especially if designed for a bulk TMSC process. Intel can finetune their designs since they build and maintains their own cutting-edge world-leading fabs.
Only Itanium mainframe CPUs have used on-die SRAM caches in the 32MB range, and possibly some other, more obscure big iron processors intended for supercomputers from makers like Fujitsu and so on. IBM's Power series either uses eDRAM for its largest-level cache I believe or separate, off-die modules.
...In a consumer device? Well, MS could have gone completely mad all of them, it's certainly within the realm of possibilities, but I wouldn't count on it. Far too great a risk for disappointment!
Ninjaprime
Regular
SRAM is a complex 6 or 8 trasistor array and is very low latency. eDRAM is just DRAM on die, a single transistor and a capactior to hold a charge. eDRAM can be 8x as dense as SRAM in some cases, however, it still needs to be refreshed unlike SRAM, and thus has much worse latency.
If its 32MB, theres no way its SRAM, clearly its eDRAM and somewhere along the way its been lost in translation. 32MB of SRAM is massive.
Still much, much better latency than off-die DRAM memory though. Also, using SRAM buffers to try and hide refresh and page miss penalties and so on like Mosys' 1T SRAM is pretty effective, alledgedly. At a die area cost though, of course...
Ninjaprime
Regular
It would be a gain, its just not possible. These chips are mostly likely 28nm, which is pretty much the same scale-wise as Intel's 32nm. The largest server chip Intel made on 32nm was Westmere-EX, and it was 10 cores and had only 30MB of L3 cache on it. The L3 array takes up, ~40% of the chip, and its a giant 513mm^2 chip. It would be ridiculous for a console to use up 200mm^2 for a 32MB chunk of cache.
For SRAM, 100 GB/s seems very low BW. The ESRAM confusion comes from some company providing a form of 1T-DRAM calling it ESRAM. 1T-SRAM is a registered trademark so cannot be used, and it may be technologists would rather call it SRAM than the more accurate DRAM as SRAM sounds faster (?).
If we look at BW and die size expectations for eDRAM and SRAM, I think it's pretty clear the memory must be a form of DRAM, just badly named for which we can probably thank Mosys for setting a lousy precedent.
If we look at BW and die size expectations for eDRAM and SRAM, I think it's pretty clear the memory must be a form of DRAM, just badly named for which we can probably thank Mosys for setting a lousy precedent.
http://en.wikipedia.org/wiki/1T-SRAM
Shifty Geezer is right, it's most likely to be 1T-SRAM renamed as Esram.
Shifty Geezer is right, it's most likely to be 1T-SRAM renamed as Esram.
Bagel seed
Veteran
Some forumers over on Semiaccurate think the chip or SoC might be a stack on SRAM. I think that kinda explains how they can integrate the huge die with everything else... Charlie says its an active interposer. In other words SRAM = Interposer. Also I don't think it needs to be 28nm in that case.