limit of NV4x's instruction count

[moichi]

http://download.nvidia.com/developer/presentations/GDC_2004/gdc_2004_OpenGL_NV_exts.pdf
This slides says:

NV_vertex_program3:
Up to 512 instructions

NV_fragment_program2:
Up to 16K instructions


I believe NVIDIA would design their new OpenGL extensions for NV4x's hardware capability.
So count of instruction "slot" would be limited.
But count of execute instruction would be no limit when branch instruction used.

I think vertex shader's instruction memory is on-chip like NV2x-NV3x,
(If off-chip, vertex shader unit would fetch instruction via vertex texture unit.)

 

[Richard]

Just guessing but wouldn't that difference come about because dx has caps while ogl doesn't?

 

[Ostsol]

Just guessing but wouldn't that difference come about because dx has caps while ogl doesn't?

Not sure what you mean by that. . . Are you refering to optional functionality and variable (by vendor) numerical restrictions (such as instruction counts)? OpenGL has the former via extensions and the latter is simply based on the implementation. The numbers themselves can be found using the glGet function.

Anyway, I'm guessing that the instruction limitation for vertex shaders is the static instruction limit. With looping the effective number of instructions able to be processed is undoubtably much, much more.

The fragment shader limitation is kinda confusing. . . Might that be the maximum effective instruction count (including looped instructions)? It'd be a bit strange to report the effective instruction count for fragment shaders and the static instruction count for vertex shaders. . . *scratches head*

What surprised me about that document was that it appears that NVidia is for the first time using ATI extension (for float textures and MRT). With this kind of support, perhaps those extensions will be upgraded to ARB status.

 

[moichi]

I think NVIDIA OpenGL software team develop NV OpenGL Extensions only for NVIDIA GPUs,
so their spec would match their hardware capbility.


NV3x's pixel shader unit fetch instruction from video memory(not on-chip memory) via texture unit like CPU.
Please see Mr.Demirug's CineFX article and NVIDIA pixel shading patent.
http://www.3dcenter.de/artikel/cinefx/index_e.php
http://l2.espacenet.com/espacenet/viewer?PN=WO02103638&CY=gb&LG=en&DB=EPD

So I think count of pixel shader is easy to extend.
It's a matter of bit width of internal program counter register.
16K instruction space can be addressed by 14bit width program counter.
(NV3x's 1024 instruction space could be addressed by 10bit width program counter.)


ATI extensions certainly supported in NV40.
http://www.beyond3d.com/previews/nvidia/nv40/index.php?p=ogl