Love_In_Rio
Veteran
Wouldn´t be in the range of 80 GFlops ? And, thus, Sony making a little variations of the chip couldn´t have reached the theorical computational power of the Xenon CPU ?
ERP said:I suspect that your average hardware engineer would consider scalinmg the clock from 300MHz to 4GHz to be more than a minor tweak.
Love_In_Rio said:Wouldn´t be in the range of 80 GFlops ? And, thus, Sony making a little variations of the chip couldn´t have reached the theorical computational power of the Xenon CPU ?
xbdestroya said:Love_In_Rio said:Wouldn´t be in the range of 80 GFlops ? And, thus, Sony making a little variations of the chip couldn´t have reached the theorical computational power of the Xenon CPU ?
I've been told that the Cell chip is actually the spiritual successor of the Emotion Engine in a lot of ways. Not knowing enough about it to get into it, I'll leave it at that. Also of course, the Cell brings to the table it's ease of scalability.
sunscar said:That would only be if the chip stayed with the same number of transistors and the same die size and the same silicon process though. How many EEs could be placed side by side in a parallel configuration with the techniques used today though? Enough to smash through the 80Gflops barrier quite easily, if it were to run at such a high clock speed.
I would think that an expert hardware engineer would consider it rather unpleasantERP said:I suspect that your average hardware engineer would consider scalinmg the clock from 300MHz to 4GHz to be more than a minor tweak.
Simon F said:I would think that an expert hardware engineer would consider it rather unpleasantERP said:I suspect that your average hardware engineer would consider scalinmg the clock from 300MHz to 4GHz to be more than a minor tweak.