IBM revision doc for SPE ISA

[chris1515]

A Document revision of SPE ISA:

http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/76CA6C7304210F3987257060006F2C44

 

[chris1515]

Moving the thread in Console technology forum

a moderator can move the thread on console technology forum

 

[compres]

This is console tech. already.

 

[chris1515]

The thread was in console talk before.

 

[Titanio]

Wasn't sure if I should make a new thread, but last week IBM put up a series of 5 tutorials regarding concerns for compilers targetting Cell, which looks like pretty interesting reading if you want an appreciation of the challenges faced (and more generally by programmers tackling Cell without some the compiler help discussed):

http://www-128.ibm.com/developerworks/power/cell/articles.html

They also talk about an implementation of a software cache for SPEs - a last resort, as they put it - mentioning that hit latency in theirs is 20 cycles.

edit - Also, there's going to be a Cell Workshop held by IBM in March:

http://www.power.org/news/events/cellworkshop/

 

[Guden Oden]

If a software cache gets a latency of 20 cycles (average, I guess), doesn't that sound rather phenomenal, considering doing a DMA operation across the ring bus has to be a major operation? I mean, how many cycles is it just to set up the DMAC?

 

[Titanio]

If a software cache gets a latency of 20 cycles (average, I guess), doesn't that sound rather phenomenal, considering doing a DMA operation across the ring bus has to be a major operation? I mean, how many cycles is it just to set up the DMAC?

The latency for a cache hit in their implementation is 20 cycles. Thus there'd be no DMA there, the data is already in the local store, in the software-controlled cache. If the data isn't there, then obviously it's like a cache miss on any CPU (with DMAs to pull the required data in + some other data, depending on the cache policy or whatever).

 

[Sct I/On]

From "optimizing compiler for a CELL processor" by Eichenberger et al.

http://cag.csail.mit.edu/crg/papers/eichenberger05cell.pdf

The DMA operations in the miss handler take several hundreds of cycles, but this delay is roughly commensurate with L2 miss timeson the PPE side of the CELL processor. The performance impact of the Software Cache is dominated by the cost of the cache probes, not by the miss cost.

 

[Gubbi]

They also talk about an implementation of a software cache for SPEs - a last resort, as they put it - mentioning that hit latency in theirs is 20 cycles.

Hey, I predicted that 10 months ago

Cheers

 

[rounin]

Wow. Even got the cycles spot on