I Can Hazwell?
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UniversalTruth
Veteran
Ask AMD when they will get their shit together. We could have had 8, 12, 16 core processors already long time ago. But no competition- no new interesting products
No. We already have 8 core Sandy Bridges (sold as Xeons only), and there will also be 12 core Ivy Bridges out this year (http://wccftech.com/intels-leaked-r...epen-processors-12-cores-30mb-cache-130w-tdp/). Haswell-E rumors are claiming 12, 16 or 20 cores for the high end parts (Xeons only most likely).
UniversalTruth
Veteran
Two mutually exclusive parts of the answer. He probably meant when the *770 parts would get 8 physical cores...
But nowadays corporations are afraid of competition. It is not something that motivates them to do better, but something which motivates them to kill the competitor by acquiring it, or doing agreements with competitors not to fight each other because of the economic interest.
Not long time ago I even read a statement of one big company claiming that the big competition in their sector kills the desire of investors to... invest...
Universal,
It's not so much a part of AMD not having its shit together, as there simply not being any need or demand for 8+ core desktop CPUs. What are you going to run on them anyway? There's no applications used by everyday people and companies that require that much oomph, and precious few situations where you really even need four cores.
Video transcoding is a relatively common such niche task, but that is taken care of by more common solutions now like intel's quickpath and GPU assist for example.
It's not so much a part of AMD not having its shit together, as there simply not being any need or demand for 8+ core desktop CPUs. What are you going to run on them anyway? There's no applications used by everyday people and companies that require that much oomph, and precious few situations where you really even need four cores.
Video transcoding is a relatively common such niche task, but that is taken care of by more common solutions now like intel's quickpath and GPU assist for example.
Yeah, that was added recently.LOL, it took me 15 sec. to realize there's L4 cache row in the AIDA memtest box.
4 more weeks... I'm rather disappointed that we haven't seen any performance previews from reputable review sites, other than the one at Tom's. If you count Tom's as a reputable review site, that is.
Well, the screencap is obviously after the load has been relieved. The voltage we see there is more than likely the idle voltage rather than the load voltage. I say that with the suggestion that the new on-package voltage regulation may be intelligent enough to modify voltage per load, as well as per clockspeed.
Pure speculation on my part, but it answers the obvious question
That would make perfect sense, and would be rather incredible.Well, the screencap is obviously after the load has been relieved. The voltage we see there is more than likely the idle voltage rather than the load voltage. I say that with the suggestion that the new on-package voltage regulation may be intelligent enough to modify voltage per load, as well as per clockspeed.
Pure speculation on my part, but it answers the obvious question
I'm not seeing it being mentioned in this slide, though. It seems to suggest that voltage and frequency are tied together, but makes no mention of load.
http://images.anandtech.com/doci/6898/Screen Shot 2013-04-12 at 5.14.38 PM.png
I suppose it could be a feature that they haven't disclosed, yet. I just imagine that that slide in particular would have been a great place to introduce it.
You're absolutely correct; I was merely pulling ideas from my posterior I cannot otherwise explain how a 5Ghz Haswell pulled that kind of stunt on only 1v ...
I cannot otherwise explain how a 5Ghz Haswell pulled that kind of stunt on only 1v ...Well, the screencap is obviously after the load has been relieved. The voltage we see there is more than likely the idle voltage rather than the load voltage. I say that with the suggestion that the new on-package voltage regulation may be intelligent enough to modify voltage per load, as well as per clockspeed.
Pure speculation on my part, but it answers the obvious question
So long as the program is running and can sample the voltage it's momentarily at 100% load. At a fine level you're always at either 100% load (active) or 0% load (idle by issuing halt instructions). While it's idle the clock is basically 0Hz (gated) and the voltage is dropped accordingly, but it's not something you can monitor while awake.
With that simple logic, we would never get an idle voltage out of any of the monitoring software out there -- which we know is patently false. I understand what you're talking about when you say the processor is either 0 or 100, but the CPU doesn't alter clock speeds like that no more than the OS kernel dictates as much.
The CPU understands transient, "partial" load just like the kernel does, and the voltage monitoring doesn't invoke "100% load" on the simplistic query for CPU utilization nor voltage delivery.
Something else that I didn't consider: the clockspeed is still indicated at 5GHz, but how many active cores are there? We know that SuperPi is single-threaded; perhaps the voltage regulation is different when not all cores are active? Maybe they can even do voltage per core? I wonder if they'd expose that capability though...
Two mutually exclusive parts of the answer. He probably meant when the *770 parts would get 8 physical cores...
But nowadays corporations are afraid of competition. It is not something that motivates them to do better, but something which motivates them to kill the competitor by acquiring it, or doing agreements with competitors not to fight each other because of the economic interest.
Not long time ago I even read a statement of one big company claiming that the big competition in their sector kills the desire of investors to... invest...
Yea , I was talking in the affordable range of say $500-$800 bucks. Heck I'd take a 6 core at this point.
Theories:
1) The image is a fake, and we're all being played for fools.
2) There's a bug with voltage reporting, and we're all being played for fools.
3) The user changed the voltage and/or clock speed on the fly, closed out the overclocking utility, and grabbed a screenshot before the system inevitably crashed. We're still being played for fools.
4) Haswell's iVR really is that big of an improvement over external VR. The electrical signal is stupid clean.
5) There's some wicked complex method of lowering voltage relative to some combination of load, temperature, or enabled/disabled circuitry.
6) There's been an intentional change in voltage reporting, and software-read voltages cross-generation are incomparable. There may be a hidden improvement, but the only way to determine this would be through probing.
#4 doesn't make much sense, because that would mean that the gains from integrating a voltage regulator would have been recognized and implemented over a decade ago. We're talking double digit percentage reductions in voltage. The chance that nobody ever thought to implement this is effectively zero, and this would still have to be rationalized against SoCs that already have an iVR.
#5 I can actually see. We already know that Intel has been toying with fine grained, dynamic voltage. This is the main point of the iVR, correct?
#6 I'm sure there's been some change in the accuracy of voltage reporting, but that wouldn't account for such a discrepancy.
1) The image is a fake, and we're all being played for fools.
2) There's a bug with voltage reporting, and we're all being played for fools.
3) The user changed the voltage and/or clock speed on the fly, closed out the overclocking utility, and grabbed a screenshot before the system inevitably crashed. We're still being played for fools.
4) Haswell's iVR really is that big of an improvement over external VR. The electrical signal is stupid clean.
5) There's some wicked complex method of lowering voltage relative to some combination of load, temperature, or enabled/disabled circuitry.
6) There's been an intentional change in voltage reporting, and software-read voltages cross-generation are incomparable. There may be a hidden improvement, but the only way to determine this would be through probing.
#4 doesn't make much sense, because that would mean that the gains from integrating a voltage regulator would have been recognized and implemented over a decade ago. We're talking double digit percentage reductions in voltage. The chance that nobody ever thought to implement this is effectively zero, and this would still have to be rationalized against SoCs that already have an iVR.
#5 I can actually see. We already know that Intel has been toying with fine grained, dynamic voltage. This is the main point of the iVR, correct?
#6 I'm sure there's been some change in the accuracy of voltage reporting, but that wouldn't account for such a discrepancy.
3930k's can be had for $500USD. I like mine
still only a sandybridge and only 6 cores
Are you sure you're not confusing DVFS w/lowered clocks and voltages with "idle voltage"? If a program is running the CPU isn't idle. But I guess it's possible that the voltage reading has a low frequency response and/or delay that can cause you to read a lower voltage if the CPU is idle most of the time.
But that's different from the VRM deliberately regulating to that voltage.
You need to put out the full voltage in order to run at full clock speed even for just small amounts of time, which is what will happen any time the thing isn't idle. The CPU is either idle or it isn't, there's never any point where you can give it some in-between voltage to meet some in-between load state. What the CPU can do - and what it would sooner do - is lower the active clock speed and the voltage needed for it. But that's not what's going on here.
The amount of cores running doesn't impact the voltage one core needs to run at some clock speed (for given environmental conditions, binning, etc). If there are separate voltage rails per core then you have to ask what rail is being reported here..
Exosphase,
Rather than playing quote hell, let's just say this: all of the Core architectures support multiple VIDs for varying loads. If the CPU only ever reported two states: zero and 100%, then we could simply never use any of the intermediate VID's outside of a forced-state. Similarly, we couldn't use the turbo states either, as "more busy" never truly happens than "less busy" in that scenario.
Processors have, for a very long time, some way of measuring computational load over time and have been able to report that as a "load percentage". An idle Intel CPU will operate at the lowest multiplier and voltage, an Intel CPU with moderate (but not peak) usage will operate at an intermediate multiplier and voltage, and a fully loaded Intel CPU will go in and out of boost depending on -- in addition to thermal and power limits -- workload.
You can view this right now on your own PC. Open up task manager, open up resource monitor, and then view the details on your CPU tab. You will see the clockspeed vary continuously depending on what you're doing, and the variance isn't binary zero to 100%.
Also consider that voltage for singular cores vs multiple cores may not need to be different per-core, however many of the 'shared bits' will be under less load during high utilization of a single core versus high utilization of all cores. Intel's own DX79Si board firmware allows for voltage variance based on number of active cores -- it also allows for speed variance per active core too. It's obviously indicating that the voltage is a "package" voltage rather than core-specific.
Rather than playing quote hell, let's just say this: all of the Core architectures support multiple VIDs for varying loads. If the CPU only ever reported two states: zero and 100%, then we could simply never use any of the intermediate VID's outside of a forced-state. Similarly, we couldn't use the turbo states either, as "more busy" never truly happens than "less busy" in that scenario.
Processors have, for a very long time, some way of measuring computational load over time and have been able to report that as a "load percentage". An idle Intel CPU will operate at the lowest multiplier and voltage, an Intel CPU with moderate (but not peak) usage will operate at an intermediate multiplier and voltage, and a fully loaded Intel CPU will go in and out of boost depending on -- in addition to thermal and power limits -- workload.
You can view this right now on your own PC. Open up task manager, open up resource monitor, and then view the details on your CPU tab. You will see the clockspeed vary continuously depending on what you're doing, and the variance isn't binary zero to 100%.
Also consider that voltage for singular cores vs multiple cores may not need to be different per-core, however many of the 'shared bits' will be under less load during high utilization of a single core versus high utilization of all cores. Intel's own DX79Si board firmware allows for voltage variance based on number of active cores -- it also allows for speed variance per active core too. It's obviously indicating that the voltage is a "package" voltage rather than core-specific.