Something's puzzling me about the RivaTuner logging image on Guru3D:
http://www.guru3d.com/admin/imageview.php?image=5265
Note that there is a distinct step down from 468MHz to 430MHz, before dropping back down to 303MHz (2D mode). One can just make out there is a similar step on the way up, but the time for the step up is significantly shorter than the time for the step down. The latter is the puzzling bit - the chip is clearly in 3D mode, as it's running at 430+ but why doesn't it stay at the higher core speed all the way to the end?
http://www.guru3d.com/admin/imageview.php?image=5265
Note that there is a distinct step down from 468MHz to 430MHz, before dropping back down to 303MHz (2D mode). One can just make out there is a similar step on the way up, but the time for the step up is significantly shorter than the time for the step down. The latter is the puzzling bit - the chip is clearly in 3D mode, as it's running at 430+ but why doesn't it stay at the higher core speed all the way to the end?
geo said:
I agree that it is odd, but there may be some influence from other factors: current fan speed etc. Lots of equipment can sense their clock/temp correctly but report it incorrectly because the 'ticker' is interpreted incorrectly (thinking mainboards reporting the wrong CPU temperature here. The temperature is always reported the same, so how can different BIOSes/BIOS revisions display different results?).
This is one reason why I would like to see if the absolute 40MHz clock differential holds true when you change the clock very far from the default (probably only possible down). It would be mighty strange to add 40MHz instead of multiplying by 10%, for example. Especially if this clock is "for something else" like people are speculating. The pipelines are obviously dependent on each other, so increasing 40MHz absolute is not going to make sense because the whole must scale together. But I suppose that is at the heart of the "conspiracy theory": that they added what they could get away with.
NV do mention that rasterization rate and triangle setup has been increased (right?). I dont know how Dave came to the conclusion that the increased stencil performance had anything to do with the shaders.
One potential bottleneck with double speed z/stencil is triangle setup/rasterization.
One potential bottleneck with double speed z/stencil is triangle setup/rasterization.
Ailuros said:
All's fair in love and graphics cards.
I could torture a rationale to call that efficiency --something to do relative to the "primary" (NV's word) clock of the card.What I'd do is be looking for an unexplained ~10% somewhere. Which in fact is what I did, going back to digit-life's review where they downclocked and disabled units on a 7800gtx to normalize to a 6800u and compared on a lot of tests. That kind of thing should have made it jump of the page. Gotta admit I'm not seeing 10% anywhere.
Neeyik said:
That "step down" is a usual low power 3D mode (or performance level 1), NV uses it since NV3x series. The target clocks of this mode can be found in VGA BIOS (captured with RT too):
$1100010000 Perf. level 0 : 275MHz/600MHz/1.20V/100%
$1100010001 Perf. level 1 : 415MHz/600MHz/1.40V/100%
$1100010002 Perf. level 2 : 430MHz/600MHz/1.40V/100%
dizietsma said:
Both 3DMark and RT read that clock from the same source - PLL registers 4000/4004. These registers were used for generating whole core clock for the previous NV4x family.
Now I cannot say for sure what are these registers for in NV47, it is still under investigation. But I can say for sure that:
1) These regs are is still in use and still reprogrammed by driver when setting core clock
2) These regs have the same format as before, so that PLL generates 470MHz with no doubts
But if I understand BIOS and the driver's internals correctly, then there are 3 different blocks in the core, which can be clocked differently. Clock frequency source of each block is switchable, all blocks are clocked from the same PLL (or clock frequency generator in other words) in 2D mode. In 3D mode clock source of 2 blocks does seem to be switched to different PLL (and it does generate the clock close to 430MHz), but the third block is clocked by the same PLL in 2D/3D modes and it does programmed to generate higher clock (470MHz instead of 430MHz).
I was investigating hypothesis of incorrect clock frequency reading from the beginning together with Ashley (the guy behind PowerStrip and Entech library used in 3DMark's clock detection), but after spending more and more time on this investigation I become more and more certain that our clock readings are correct and there is really something in the core clocked differently comparing to pixel pipes. ASUS just virtually confirmed us yesterday with that "Geometric clock delta" announce, NVIDIA in fact did the same by mentioning complex clocking of NV47 core and its' primary clock. Anyway, I still analyze the driver and the time will definitively show if our assumption is correct or not.
P.S. If my understanding is correct and some parts of core are really clocked differently, then I don't understand why NVIDIA refers to 430MHz in their reply as to a primary core clock. As far as can understand the driver now, the clocks I mentioned above are not derived from one "primary" core clock and generated by completely independent multipliers.
Can't get much more of an educated answer on that one than you, can I?Unwinder said:
Thanks Unwinder, I'm curious to know what you think it is. Do you think it's a hidden design feature or more of a case of hanky-panky to make the chip look better at a lower clock?
I'm not doubting what you said, I know you're pretty much the authority on that...I'm just curious as to the why's of it now since as everyone pointed out all the tests show the card working as a 430Mhz one, but how can they if it's working at 470Mhz?
I'm clueless but figured you'd be a great person to ask.
Thanks for your answer and thanks in advance for any clarity you could bring to this for me.
EDITED BITS: I crossposted with your last post, I think you answered some of me questions...at least from what little of it I can understand, this could take me a while.
Unwinder said:
My guess is that "primary" wasn't meant to be a technical answer, but rather a marketing answer --that the 2-out-of-3 area it is controlling is the primary performance determiner for the chip. Which would lead one to think PS and VS, tho that "geometric" bit still smells like vs, even tho I can't find any vs results to support that.
At the same, if I understand you correctly, they left the 470 clock where you were used to seeing the clock from NV40 and put the 430 clock somewhere new? This would argue against the idea that there was any great scheme to hide it, or it would have been the other way 'round.
Edit: Come to think of it, have you been able to gain control of that clock independant of the 430 clock, even if the driver/bios still adds another 40 on top of whatever you put there? Manipulating both clocks (or all three) different directions more or less independantly (except for whatever the "add" is) should create some interesting results.
From reading Unwinders reply above it initially sounded to me that maybe they were boosting the ROPS because they have not got a 1:1 with the internal pixel pipelines, but I recall that Rys, or maybe somebody else saying the tests do not confirm this.
Very puzzling, but also very intereting. Curisor and curisor . Anyone know an Asus contact, that would clear it up quickly if nvidia are being silent. Asus have a very clever set of engineers, the work they did with enabling PAT on 865 and bypassing other Intel clock restriction mechanisms shows this. I wonder what smart Doctor shows on the 7800GTX ?
I assume they have the same level of boost for all 3d apps, or does it vary, say like between DX7 / DX8 and DX9 to try and optimise down to that level of granularity...
Very puzzling, but also very intereting. Curisor and curisor
. Anyone know an Asus contact, that would clear it up quickly if nvidia are being silent. Asus have a very clever set of engineers, the work they did with enabling PAT on 865 and bypassing other Intel clock restriction mechanisms shows this. I wonder what smart Doctor shows on the 7800GTX ?I assume they have the same level of boost for all 3d apps, or does it vary, say like between DX7 / DX8 and DX9 to try and optimise down to that level of granularity...
Kombatant
Regular
geo said:
I think this is essentially the answer; since the different PLL that generates the clock for these two blocks in 3D mode remains at 430MHz, a "primary clock" label for the 430MHz value seems natural to me. What I wanted to ask is whether Unwinder has investigated this PLL's behaviour in 2D mode; is it inactive? Or is used for something else? Plus, about the mention of three blocks in the core; what parts of the core do they represent? What job do they do?