Hi all,
I figure you guys know far too much about GPU's and the finer details of the hardware side of things to be healthy...
So, I work on the application side of things - I write my HLSL code and compile it to variations of 4 main targets (SM 1-4).
My general understanding is that the ATI/Nvidia drivers will translate what Direct3D feeds it into the appropriate binary/micro-code suitable for the GPU in the system. That the hardware will see a common set of GPU-specific instructions and not really have any knowledge of what shader model (be it HLSL or GLSL) or API it actually originated from.
The only case where it'd (possibly) know about any SM specifics is if the driver forced any restrictions on resolution and clamping.
Would that be a reasonable assumption?
This is kind of related to a bug I fixed today. Developed my code on an ATI chipset, everything was fine. Dropped it onto an NV card and it all went wrong. Bit of debugging later and it turns out that the NV implementation was correct according to the standards - it clamped SM1 outputs to [-1,+1] whereas the ATI implementation didn't.
Got me wondering about the IHV differences - does ATI just offload a number of instructions and leave it there and NV does the same but (where appropriate) clamp the results...
Anyone got any insight as to what that piece of silicon in my machine(s) actually end up seeing?
Cheers,
Jack
I figure you guys know far too much about GPU's and the finer details of the hardware side of things to be healthy...
So, I work on the application side of things - I write my HLSL code and compile it to variations of 4 main targets (SM 1-4).
My general understanding is that the ATI/Nvidia drivers will translate what Direct3D feeds it into the appropriate binary/micro-code suitable for the GPU in the system. That the hardware will see a common set of GPU-specific instructions and not really have any knowledge of what shader model (be it HLSL or GLSL) or API it actually originated from.
The only case where it'd (possibly) know about any SM specifics is if the driver forced any restrictions on resolution and clamping.
Would that be a reasonable assumption?
This is kind of related to a bug I fixed today. Developed my code on an ATI chipset, everything was fine. Dropped it onto an NV card and it all went wrong. Bit of debugging later and it turns out that the NV implementation was correct according to the standards - it clamped SM1 outputs to [-1,+1] whereas the ATI implementation didn't.
Got me wondering about the IHV differences - does ATI just offload a number of instructions and leave it there and NV does the same but (where appropriate) clamp the results...
Anyone got any insight as to what that piece of silicon in my machine(s) actually end up seeing?
Cheers,
Jack