Did anyone every figure out why R600 has a 512-bit bus?

[nicolasb]

What's it for?

It surely can't just be because ATi engineers lack the imagination to think in numbers that aren't powers of 2, can it?

And yet, R600 really doesn't seem to get a great deal of benefit from all that bandwidth. For RV670 (according to rumours) we're looking like an R600 on 256-bit bus running at close-to-R600 speeds. The things that you would expect R600 to be able to do with the bandwidth (high AA and AF) are actually its greatest weaknesses. So: what as ATI thinking?

 

[INKster]

What's it for?

It surely can't just be because ATi engineers lack the imagination to think in numbers that aren't powers of 2, can it?

And yet, R600 really doesn't seem to get a great deal of benefit from all that bandwidth. For RV670 (according to rumours) we're looking like an R600 on 256-bit bus running at close-to-R600 speeds. The things that you would expect R600 to be able to do with the bandwidth (high AA and AF) are actually its greatest weaknesses. So: what as ATI thinking?

Marketing ?

 

[tongue_of_colicab]

Maybe to figure out how to do it right? build a 512bit card now while the card doesnt really make use of it but in that way make sure that your next card, that will need it you dont have any (or less) problems using a 512bit bus?

 

[Bouncing Zabaglione Bros.]

For feeding the very high frequency clocks that the R600 turned out not to be able to support. I suspect it might also end up being a proof of concept that we'll see again when they start putting multiple chips on a card. When the RV670 x2 arrives, it should be 2x256mbit if a single chip needs 1x256mbit, so maybe 1x512mbit won't be too far a stretch at some point in the future, or maybe even R700.

 

[INKster]

Maybe to figure out how to do it right? build a 512bit card now while the card doesnt really make use of it but in that way make sure that your next card, that will need it you dont have any (or less) problems using a 512bit bus?

That would be a very expensive (and very public...) way of conducting "experiments".

 

[tongue_of_colicab]

Isnt that why they'll make a RV670 with 256bit bus?

 

[INKster]

Isnt that why they'll make a RV670 with 256bit bus?

I don't follow...
What does one have to do with the other ?
RV670 ("V" as in Value, i guess) is a mainstream product, it was designed that way.
Not so with R600.

 

[fellix]

As SirEric mentioned a while ago, the R600 marchitecture is 64-bit "granularity" optimized in almost every general direction, so they opted out for 8*64-bit access pattern to the local memory. And, yes - there is/was a bit of benchmarketing involved here, as it's clear that the pure fill-rate numbers aren't going to bloat this uber wide interface, but could you really believe, someone would design so complex PCB just for the numbers on the advertising slide?

And now the geek's quiz: "Hey, how about that massive stream-out & vitalization thingie, that those 64*5D shaderz were suppose to cap this 100+GB/s path..."?

 

[swaaye]

R600 is "optimized"?

 

[no-X]

The question is not "why", but "why not". It seems, that implementation of 512bit memory interface wasn't more difficult for ATi, than implementation of 384bit bus for nVidia. HD2900XT's PCB is even shorter. I think the main reason was uncertain situation with fast GDDR4, which would be necessary for 256bit part. And the last reason - 512bit bus isn't necessary, but I think it helps occasionally (e.g. when XT is on par with GTX/Ultra).

 

[dizietsma]

There's a very simple answer to this

The previous card had 512bit bus and had GDDR4 memory, so if AMD had released a card with 256bit bus and GDDR3 memory people would have thought what? Hello Mr MidRange!

Big numbers sell cards at the end of the day, even if nobody actually knows what they relate to in real life.

 

[fellix]

Err, which "previous" card?

 

[hoom]

Surely its because ATI hadn't expected GDDR3 to scale as high as it did nor that GDDR4 would arrive as soon as it did. (also for R600 to be as late as it was, similar effect)

Put lower speed GDDR3 on an R600 & you would get a total bandwidth similar to high end 256bit GDDR3 or for RV670 GDDR4.

 

[Jawed]

Surely its because ATI hadn't expected GDDR3 to scale as high as it did nor that GDDR4 would arrive as soon as it did. (also for R600 to be as late as it was, similar effect)

You'd think this except that ATI was closely involved in the development of both GDDR3 and GDDR4 (and GDDR5, it seems) - judging by patents, anyway...

Jawed

 

[hoom]

Being heavily involved in writing up the spec doesn't necessarily mean that they knew when/how high it was going to scale in manufacturing from as far back as they would have made a decision to go for 512bit.

 

[INKster]

Being heavily involved in writing up the spec doesn't necessarily mean that they knew when/how high it was going to scale in manufacturing from as far back as they would have made a decision to go for 512bit.

I agree.
ATI having such a deep involvement at the early stages of R&D of a particular type of memory doesn't mean they could have guessed that GDDR3 would end up reaching 2.4GHz+ (used as such in a competing product, in this case the 8800 Ultra), and that it would be so pervasive against GDDR4 in the market for so long.
I already have my doubts that Nvidia will ever use GDDR4, and not skip from GDDR3 right up to GDDR5.

 

[Jawed]

Being heavily involved in writing up the spec doesn't necessarily mean that they knew when/how high it was going to scale in manufacturing from as far back as they would have made a decision to go for 512bit.

You're asserting that both GDDR3 wouldn't continue scaling and GDDR4 would be late, when the trend was for GDDR to scale well (GDDR3 wasn't much faster than GDDR2 when it first appeared - because GDDR2 kept on scaling) and for GDDR to arrive in good time (NVidia had GDDR3 graphics cards on the market before 6800U/X800XT launched, the first cards that were ostensibly dependent upon GDDR3 to get their required bandwidths).

I think the best explanation for 512-bit is that ATI wanted to try out a high-density memory interface on the package - in my view ATI's going to want that high density when putting two RV670s onto one package. But maybe they'll be boring and keep the two on separate packages. Maybe it's R700 that's due to make that leap, putting both GPUs on one package? Erm...

ATI did something similar with the R5xx memory controller. The (asymmetric) ring bus introduced at that time evolved into the symmetric ring bus we have now. That was an "experiment" too, I reckon: R580 seems to have far more bandwidth than it can usefully use (compare it with 8800GTS with exactly the same bandwidth...).

Jawed

 

[wingless]

When you overclock with cascade liquid nitrogen to 1200+mhz for 3DMark06 world record breaking sessions the bandwidth will be used.
A 512-bit bus with over 100GB of bandwidth sure isn't considered a bottle neck on this card is it? Why the hell are we having this conversation. Personally I love blatant overkill and brute force approaches. I wish more of the R600 had been designed with that kind of thought process. I bet current Nvidia cards would love these huge buses. BTW, I read that Nvidia G9X performance cards will have 512-bit buses so Nvidia thinks that too.

 

[CarstenS]

Marketing ?

Saving on R&D?

 

[Davros]

because 511bit would just be silly wouldnt it