Chips pass two billion transistors

[Davros]

Actually if you magnify that picture felix posted you will discover that the intel engineerrs are fans of a space sim called freespace

 

[silent_guy]

It's there, but it drains out really fast. That's why most chips don't only have an upper speed, but a lower speed as well, which is often more than half the specified speed.

Huh?

This would only be true for certain types of custom dynamic logic, but there's pretty much nobody who uses that anymore. Maybe some CPU's...

Lower bound clocks speeds are usually due to architecture decisions or issues when talking to logic blocks that are still running on a faster clock.

 

[silent_guy]

But it's still just a 2D layout; when do we start talking about "stacking" silicon layers?

The major problem is that a large part of your transistor characteristics are defined by the initial slab of silicon on which everything is built up. There are currently viable techniques to grow a pure bulk silicon layer on top of the silicon oxide layer which is used as the isolation between metal wires.

(And then there are, indeed, the other factors that Frank pointed out.)

So either you'll have to come up with something completely new, or you'll have to somehow glue 2 separately processed wafers together. Which is probably not what you had in mind...

 

[Sc4freak]

The major problem is that a large part of your transistor characteristics are defined by the initial slab of silicon on which everything is built up. There are currently viable techniques to grow a pure bulk silicon layer on top of the silicon oxide layer which is used as the isolation between metal wires.

(And then there are, indeed, the other factors that Frank pointed out.)

So either you'll have to come up with something completely new, or you'll have to somehow glue 2 separately processed wafers together. Which is probably not what you had in mind...

Wasn't Intel planning to bolt on a slab of DRAM on top of their CPUs at one point?

 

[Thorburn]

Wasn't Intel planning to bolt on a slab of DRAM on top of their CPUs at one point?

I think underneath, but certainly something to that effect.

 

[silent_guy]

Wasn't Intel planning to bolt on a slab of DRAM on top of their CPUs at one point?

Maybe for some of their upcoming mobile CPU's? Die stacking has been around for years, but it's not usable for high power stuff.

 

[ShaidarHaran]

I know it had been discussed for Polaris at least.

 

[dkanter]

The major problem is that a large part of your transistor characteristics are defined by the initial slab of silicon on which everything is built up. There are currently viable techniques to grow a pure bulk silicon layer on top of the silicon oxide layer which is used as the isolation between metal wires.

(And then there are, indeed, the other factors that Frank pointed out.)

So either you'll have to come up with something completely new, or you'll have to somehow glue 2 separately processed wafers together. Which is probably not what you had in mind...

Actually to be perfectly honest, I expect that the first manufacturing technique will be bonding separate dice together. It sounds much smarter for the first generation:

This article pretty thoroughly covers 3D integration based on a discussion at MICRO:

http://www.realworldtech.com/page.cfm?ArticleID=RWT050207213241


More on topic of tukwila:

I expect yields to be fairly good, considering that there is redundancy for the SRAMs. Also, while each Tukwila is the size of probably 4-5 Meroms, each Tukwila probably brings more to Intel's bottom line than all 4 of those Meroms.

David

 

[randomname]

End of the game?

Pass the sauce! It's going to be a bumper season.

I was curious, if transistors per mm^2 double every 2 years, what are the practical limits for this type of technology? 11nm? 6nm?

Intel researchers claimed already in 2003 that below 16 nm you cannot get around quantum tunneling, no matter what materials are used.

"
When the length of the gate gets below 5 nanometers, however, tunneling will begin to occur. Electrons will simply pass through the channel on their own, because the source and the drain will be extremely close. (A nanometer is a billionth of a meter.)
...
In chips made on a 16-nanometer technology process, the transistor gate will be about 5 nanometers long.
...
"You could probably go to 4" nanometers, he said, but that would require increasing the energy needed to run the chip to make the barrier less susceptible to tunneling.
"

http://news.zdnet.com/2100-9584_22-5112061.html

But that is just one aspect in the scaling down processors, and I do not know if the maximum density for the other parts of the circuitry is achieved at the same point. Nevertheless, my current computer has a 130 nm CPU (Athlon XP) and GPU (R9800), and 45 nm processors are starting to come out now. It will be as many process technologies from 45 nm to 16 nm, so the end of this particular game appears to be coming soon enough (too soon?). [Even with possible 3D stacking of transistors, this should set some kind of a limit on processing power per watt.]