Chips pass two billion transistors
- Thread starter Davros
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As far as I remember, the lattice constant of silicon is like 0.5 nm. This is basically the lengths of a cubic unit cell where on the average 8 Si atoms reside in a crystal like shape.
I think we might see more nano-type circuit elements at those scales, like tubes and tunneling junctions.
Not only do you run into the atomic granularity / "resolution" issues, but I also recall reading that you run into quantum mechanics issues where electrical charges start disappearing / reappearing / routing on their own after a certain point.
Though I could've understood wrong, a bunch of that info was WAAAYYY over my head.
Though I could've understood wrong, a bunch of that info was WAAAYYY over my head.
I think my brain boiled "quantum tunneling" down into more "shit goes everywhere and you don't always know it" sorta concept 
Well, it comes down to probabilities and wave equations ergo Quantum Tunneling.
*makes Duhhrrr face*
Actually I suppose I give myself less credit than I deserve; most of it makes sense, I just can't always understand all of it. Hell, I can't even explain some of the parts that I don't understand. But anyway, I'm gonna stop talking about my lack of quantum brain capacity because I'm just dragging the thread off-topic.
Back to the original topic.
At 65nm, that has to be a monster of a chip. But it's still just a 2D layout; when do we start talking about "stacking" silicon layers? Do they still count as a single "chip" when you do that? And of course, we're ignoring the thermal issues that become such a BIG issue when size goes down and power consumption goes up due to the hojillion trannies that need to keep switching.
Finally, how much capacitance do you suppose that many transistors has? That chip has to have like a half-farad
of electrical capacitance from all the parts inside. You know if you could somehow yank it straight out of a running motherboard and lick the back pads, you'd expect a 1KVA shock Golem.de says it is 21,5 x 32,5 mm with 2.05 billion transistors, so indeed, it is large.
Source, in German: http://www.golem.de/0802/57511.html
Source, in German: http://www.golem.de/0802/57511.html
Intergration! Thats the word isn't it? How about combining Folding at home with a radiator and 20 P4@3.5GHZ chips. Wouldn't that be a good way to both heat your room, save peoples lives by assisting in medical science and recycle old chips?
From an overall work output perspective, yeah. From a energy consumption versus output perspective, probably not
But you've got the recycling twist in there too; I'm not sure how you quantify that piece of it...That chip IS a monster mofo though!
I have to assume a chip of that size is a serious pain in terms of defect rate. Makes you wonder how much of that transistor count is for redundancy sake to make sure you don't have to throw away two-thirds of a square centimeter of silicon wafer? Yeouch.
Silent_Buddha
Legend
Are those to scale? Holy hell you could fit approx 5-6 conroes in that space.
Regards,
SB
Regards,
SB
I'm having flashbacks of the original Pentium Pro chips -- remember how ginormous those things were? Like 2 square inches I remember the first time I saw one, flipped it over and saw all those gold pins, I was in awe...
And just think how much smaller a 45nm Wolfdale is compared to the picture above...
I remember the first time I saw one, flipped it over and saw all those gold pins, I was in awe...And just think how much smaller a 45nm Wolfdale is compared to the picture above...
They already do. Generally, you have a single layer of transistiors, with multiple layers of wires.
Why they don't stack it even more has multiple reasons.
First, heat: they have to be able to get rid of all the heat it produces, which is already the main problem. You could decrease the clockspeed, but who wants that?
Second: process complexity. The walls of the "channels" that are created on the chips aren't straight, but tapered. And the top of each layer is more irregular than the last, which means that they have to step up the size of the structures for each new layer. Diminishing returns and more chances for faults.
And third: the pin count goes up as well, and pads to attach pins are relatively huge and should be positioned at the sides, or on a separate layer with lots of huge pads and ample spacing between them.
It's there, but it drains out really fast. That's why most chips don't only have an upper speed, but a lower speed as well, which is often more than half the specified speed.Finally, how much capacitance do you suppose that many transistors has? That chip has to have like a half-farad
I'm having flashbacks of the original Pentium Pro chips -- remember how ginormous those things were? Like 2 square inches
And just think how much smaller a 45nm Wolfdale is compared to the picture above...
Not a dieshot, but side by side of 5 Intel mobile CPU cores here.
Is this thread in the right place? Processor & Chipset Technology sounds more relevant.
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