Best of: Latest Kutaragi Interview (HDD, blu-ray, RSX)

[Carl B]

Here's the latest interview with Kutaragi: Gamespot

Full text may also be seen in the Sony PR thread


Some of the things I came away with:

1) It seems that Kutaragi is dreaming up uses for Cell's that don't make the 7-SPE cut-off for PS3, siggesting the possibility of dual-Cell equiped home server down the line with two 6-SPE chips.

2) Puts to rest the notion of the 'redundant' SPE being for anything other than yield purposes. (how could people have doubted for so long?)

3) Suggests they could go 4 GHz if they really wanted, but the resultant cooling considerations would force the size of the actual unit to greatly increase; basic implication being that the current PS3 prototype will be roughly the size of the eventual final unit.

4) States the RSX will use the same 'aesthetic' as the Cell with it's SPE's; ie there will be portions of the die deactivated post-fab. Makes me wonder how many pipes the RSX is, what amount of pipes they are planning on deactivating, or if it's somethign else entirely they're talking about. For now though I'll bet on a 32-pipe design with 4 pipes deactivated.

5) Implies the HDD will not ship standard, and gives an entry target of 80 GB. Reiterates that Linux for Cell will ship on every hard drive, and says that DVR functionality in the HD era would require massive storage, beyond what a current hard drive could provide (more Cell storage allusions? - what IS Cell storage anyway?) - more than a TB of storage necessary.

6) Says that they are pushing ahead with blu-ray for PS3 and can no longer wait for a unified format, but should a unified format be adopted and make use of blu-rays physical structure, they will be able to accomodate it's inclusion up to Spring of 2006.

 

[EpicZero]

The HDD may not be standard...I'm really wondering if Sony is completely unaware as to how their PS2 add-on flopped.

 

[Acert93]

4) States the RSX will use the same 'aesthetic' as the Cell with it's SPE's; ie there will be portions of the die deactivated post-fab. Makes me wonder how many pipes the RSX is, what amount of pipes they are planning on deactivating, or if it's somethign else entirely they're talking about. For now though I'll bet on a 32-pipe design with 4 pipes deactivated.

My bet is 32 with 8 disabled (thus 24 pipe).

Interestingly CELL, RSX, and Xenos (both the GPU and eDRAM cores) are said to have redundancy to enchance yields.

It makes me curious if, possibly, the XeCPU is a 4 core CPU with 1 disabled? Obviously yields are very important and it seems the manufactures have got a good handle on designs that are friendly in this area. With the size of these chips they need it! :?

 

[Carl B]

My bet is 32 with 8 disabled (thus 24 pipe).

Interestingly CELL, RSX, and Xenos (both the GPU and eDRAM cores) are said to have redundancy to enchance yields.

It makes me curious if, possibly, the XeCPU is a 4 core CPU with 1 disabled? Obviously yields are very important and it seems the manufactures have got a good handle on designs that are friendly in this area. With the size of these chips they need it! :?

I was thinking only four pipes because they wouldn't need to differentiate themselves as much as video cards in the same line - thus their concern would be purely from a fabbing perspective. I could see it being 32--->24 as well, but it seems to me that if the majority of chips would only have one defect per die, than might a well get another four pipes active.

 

[one]

It makes me curious if, possibly, the XeCPU is a 4 core CPU with 1 disabled?

If a core in Waternoose is comparable to Cell's PPE, it won't make sense 4 core chips as it's just too big. Also, there's no product for a 4 core Waternoose processor which is highly customized for XBOX 360. For Cell, 1/9 of the die area can contain a defect, but to disable 1/4 is not economically feasible and doesn't make sense as you can get more chips by simply making a 3 core CPU rather than a huge 4 core chip.

 

[phat]

My bet is 32 with 8 disabled (thus 24 pipe).

Most of the gain in yield will come from disabling the first one or two, so I doubt we'll see that many units disabled.

It makes me curious if, possibly, the XeCPU is a 4 core CPU with 1 disabled?

I'm going to assume that XeCPU will have the three cores on three dies, so the notion of shipping with a defective core disabled doesn't really apply.

Phat

 

[Chandler]

hard to do DVR when you would have to add a tuner too...so yeah that wouldnt work out.

 

[Carl B]

hard to do DVR when you would have to add a tuner too...so yeah that wouldnt work out.

Very good point.

 

[pegisys]

I'm going to assume that XeCPU will have the three cores on three dies, so the notion of shipping with a defective core disabled doesn't really apply.

could it be on three dies, wouldn't it need to be one die if they are going to share the cache

I think they are making a mistake about the harddrive also but the system cost is probably high already, and they can't price it reasonably with it included, but I can see it selling if they make it worth while to buy, but I don't think installing linux on it is going to be enough for the avg. user, and it takes all the fun out of for the geeks

 

[Bobbler]

It makes me curious if, possibly, the XeCPU is a 4 core CPU with 1 disabled? Obviously yields are very important and it seems the manufactures have got a good handle on designs that are friendly in this area. With the size of these chips they need it! :?

I have my doubts. The XCPU isn't going to be near the transistor count that the Cell/RSX/Xenos are -- even if each core on the Cell is 2x the transistor count of the PPE on the Cell it won't break 200m transistors (probably closer to 100-150m most likely) -- with that kind of count you're going to get pretty good yields without any sort of redundancy. All signs point to the fact that the cores on the XCPU are similar to the PPE on the Cell -- 3x of those + 1mb of cache isn't going to be a ton of transistors.

I get this feeling that the XCPU isn't actually a very big chip -- certainly not the transistor monster Cell is, let alone RSX/Xenos.

 

[Fafalada]

States the RSX will use the same 'aesthetic' as the Cell with it's SPE's

Unless there's another interview I'm missing, he doesn't. The only thing I found in that interview is that he states RSX will be the same as Cell in regards to being introduced on 90nm, as 65nm will not be viable for mass production in time.

probably closer to 100

1MB of L2 cache alone will probably be close to 70-80M transistors.

I get this feeling that the XCPU isn't actually a very big chip

This can be extrapolated reasonably well - a chip with 3 PPE (from Cell D2 rev) cores and 1MB of L2 looks to be in neighbourhood of 200mm2.
Sounds like a pretty big chip to me, and people are suggesting X-PPEs should be larger then those in Cell, which would make it bigger yet.

 

[Shifty Geezer]

In the Gamespot Summary the say KK mentions RSX using inbuilt redundancy for yields. Might be a naff translation though?

 

[Sis]

States the RSX will use the same 'aesthetic' as the Cell with it's SPE's

Unless there's another interview I'm missing, he doesn't. The only thing I found in that interview is that he states RSX will be the same as Cell in regards to being introduced on 90nm, as 65nm will not be viable for mass production in time.

From the Sony PR thread:

"But by considering one or two SPEs as a redundancy from the very beginning, we can still use a Cell chip even if it's partially defective," Kutaragi said, who also revealed that a similar scheme would also be used for the PlayStation 3's RSX graphics processor.

.Sis

 

[jvd]

Both ati and nvidia can do dvr functions through usb . I wonder if ati will have sole rights to this on the x360. Thier usb aiw would work very well with this set up . Mabye a bundle of a bigger drive + the aiw for a certian price
?

 

[mckmas8808]

This is a question from someone else from another forum.

But when the fabrication process becomes good enough that the Cell has all eight SPEs fully functional, will they electronically lock one SPE to make it unusable or ship it as is ?

And if they ship it with all 8 working SPEs, will your games be written to use only 7 SPEs or will your software adapt to use the power available ?

Does anyone have the answer?

 

[jvd]

They simply wont use it , most likely lock it or at that point spin another isa that is just a 1x7 . I'm sure for the next year or two they will be using the prime ones that do 1x8 for other uses and those that do 1x6 or less for other uses as needed .

 

[Carl B]

Exactly - they can't just change the spec and have later PS3's bringing more power to the table. Though the 8-SPE Cell's will doubtless become commonplace yield-wise come 65nm and beyond, PS3 will forever have Cell's with one SPE disabled.

 

[Sis]

Exactly - they can't just change the spec and have later PS3's bringing more power to the table. Though the 8-SPE Cell's will doubtless become commonplace yield-wise come 65nm and beyond, PS3 will forever have Cell's with one SPE disabled.

Right, and I thought I read somewhere that KK was expecting a large percent of the early chips will have all 8 SPEs functional (95% is stuck in my head--but I can't find the quote). So the impression I got wasn't that they couldn't produce them now, but that by including "defective" chips with 7 SPEs gives a much greater yield. So it appears to me they are already dealing with turning off, by default, good SPEs.

My comment is:
I initially took this as spin but the more I thought about it the more I agreed with KK--it does seem elegant to design the chip with redundancy and defect-protection built in.

But while it makes sense early on when they are trying to get a high yield of chips, the longer the life of this chip, the more expensive this redundancy seems to be. Once they perfect the process, or whatever, it appears that by having useless SPEs built in to every chip is just a waste.

However, the lack of interest KK's comment has generated makes me believe that it isn't necessarily a new concept and the waste issue already known. So perhaps this may just be my ignorance showing.

.Sis

 

[Npl]

Games likely wont use it, though its interesting if theres gonna be a lock at hardware-level.
If the defective SPU is disabled dynamically due selftests or information in the Flash from within Games, you could still use all 8 of them from Linux?

 

[Carl B]

@Sis: Yeah this does indeed happen all the time int he world of.. well, GPU's mostly. But it's true that the Cell is in a slightly different boat because it's total lifespan will be much greater than any GPU's. So in fact there will be a lot of cumulative wasted SPE's throughout it's life. Still, one SPE takes such a relatively low transistor count compared to the rest of the chip that clearly Sony felt this was the best way to go to ensure a proper launch.

@Npl: I think they'll have to hardware lock the 8th SPE throughout the life of the console, otherwise you get customers who purchased a PS3 with 7 SPE's with the possibility of suing to get theirs exchanged for an 8-SPE version, claiming 'defective' goods.