Yes we are!I think this graph sums up the potential performance prospect of PS5 pretty well. A mid to slightly high-ish range heavily customized card as usual per console business, that out performs a 12.7tf Vega 64 which explains the need for a 12.9tf devkit (possibly OCed Vega 64) to simulate the final performance of a Navi based 7.5-8tf console. 8 TF PS5 is true after folks and we are going to like it aren't we?
I think this graph sums up the potential performance prospect of PS5 pretty well. A mid to slightly high-ish range heavily customized card as usual per console business, that out performs a 12.7tf Vega 64 which explains the need for a 12.9tf devkit (possibly OCed Vega 64) to simulate the final performance of a Navi based 7.5-8tf console. 8 TF PS5 is true after folks and we are going to like it aren't we?
I think this graph sums up the potential performance prospect of PS5 pretty well. A mid to slightly high-ish range heavily customized card as usual per console business, that out performs a 12.7tf Vega 64 which explains the need for a 12.9tf devkit (possibly OCed Vega 64) to simulate the final performance of a Navi based 7.5-8tf console. 8 TF PS5 is true after folks and we are going to like it aren't we?
Please don’t do it this way. It’s much too confusing.
It's what Sony claimed would be used in the patent. The main point of that claim that the translation table (and perhaps some data in-flight) is on-die, obviating the need for a large external memory pool and the lower bandwidth of its interface. Even if SRAM proves more sensitive, if it's on-die I don't know what other equivalent options would be available at this point besides SRAM.I've not been following any 'technical discussion' in this nonsense thread but from a physicality POV you do not want SRAM anywhere near the a high bandwidth solid state I/O controller given SRAM is particular sensitive to signal noise. We've learnt this the expensive way.
I would suspect it's difficult to have anything besides an SRAM buffer, if it's on-die. eDRAM doesn't have a source at a modern node, and other options often have specific nodes or have limitations in terms of endurance, capacity, or performance.
Random thread perusal, and this patent had come up in other threads before. It's interesting to me in the context of the rumor about a devkit in that it's not often that an architectural element like block addressing and file system can have (or not have) externally visible consequences on a PCB.
This is true and all especially with Nvidia tossed into the equation, I still think it's somewhat reasonable to apply it just for Vega vs Navi comparison seeing how the latter is consistently equaling and out performing the former despite a Tflops deficit. Yes, we're only looking at current gen games here, who knows how the next gen game design could shift the % a bit, but I get a feeling they'll be designed with Navi in mind anyway knowing the consoles will be using those and they dictate the vast majority of the industry anyhow.
I also think the word Niche is only in relative term, compared to previous gen consoles it indeed is, but not so much compared to gpus from 2020. Unless Sony surprise the shit out of us by introducing a $599 console again with 10TF+ Navi, 16GB HBM all cooled by a monster vapor chamber, the chance of that happening is less than 5% the way I see it.
I thought Zen 2 had 32 MB of L3 cache.
