technonick
Newcomer
I keep on forgetting and need to be reminded 
Are pentium 1,2,3,4 and Athlon chips Risc Processors or Cisc
- Thread starter technonick
- Start date
No, they are not. most of them (if not all) have a risc-like core. Microcode doesn't exist anymore. A translation layer from x86 ISA to the internal ISA let the risc core execute the x86 instructions.
BTW, Cisc and RIsc CPUs doesn't exist anymore, we should talk about post Cisc and post Risc. Nowadays CPUs architectures are hybrid, and those acronyms loose the initial meaning cause so many years has passed..
ciao,
Marco
BTW, Cisc and RIsc CPUs doesn't exist anymore, we should talk about post Cisc and post Risc. Nowadays CPUs architectures are hybrid, and those acronyms loose the initial meaning cause so many years has passed..
ciao,
Marco
They are hybrid chips (except the Pentium 1). Most CISC x86 instructions (the common ones) are broken down into ROPS/RISC86 (AMD K5/K6 & Athlon) or RISC-like micro-ops (Pentium Pro/P6 and higher).
The x86 chips had features like OOO (out of order execution) and super-scalar execution (more than 1 op retired per clock cycle) before those features were adopted into RISC processors.
It's not easy to call modern desktop CPUs pure RISC or pure CISC anymore. Both share a lot in common architecture-wise.
The x86 chips had features like OOO (out of order execution) and super-scalar execution (more than 1 op retired per clock cycle) before those features were adopted into RISC processors.
It's not easy to call modern desktop CPUs pure RISC or pure CISC anymore. Both share a lot in common architecture-wise.
They are CISC.
The fact that they use some RISC techniques doesnt mean they are RISC.
The IA-32 architecture has many flaws and was not designed for maximum performance (the latest meaning for RISC is designed for performance).
It doesnt mean they are slower than some comercial RISC. It means that they are slower than a pure RISC architecture using the same technology, process manufacturing, power dissipation and die size.
See some David Patterson and John Hennessy articles/books.
The fact that they use some RISC techniques doesnt mean they are RISC.
The IA-32 architecture has many flaws and was not designed for maximum performance (the latest meaning for RISC is designed for performance).
It doesnt mean they are slower than some comercial RISC. It means that they are slower than a pure RISC architecture using the same technology, process manufacturing, power dissipation and die size.
See some David Patterson and John Hennessy articles/books.
The key point about CISC vs RISC is instruction set. Note that CISC stands for "complex instruction set computer" and RISC stands for "reduced instruction set computer", thus the key differernces between them is instruction set (or ISA for short).
Therefore, since all x86 CPUs (including all Pentiums) uses x86 ISA which is definitely a complex instruction set, they are all CISC. How they managed to run those complex instructions does not matter.
Therefore, since all x86 CPUs (including all Pentiums) uses x86 ISA which is definitely a complex instruction set, they are all CISC. How they managed to run those complex instructions does not matter.
pascal said:
Could you point to any modern pure RISC processor that is faster than current x86 processors? By definition, a pure RISC processor is not super scalar, nor does it support OOO execution. No one said x86 is RISC.
pcchen, it does matter. x86 has a CISC instruction set, but the modern processors that run it (P6 and up, K5 and higher, VIA and Transmeta) all have RISC execution engines. CISC decoders (to RISC-like ops) and RISC execution engines. That's clearly a hybrid design.
Well, it is somehow a definition problem. But since there is no clear definition for CISC and RISC, I prefer to restrict their meanings purely on instruction set, not architecture. Note that there is no way to directly access the internal RISC-like cores in most (if not all) modern x86 CPUs.
You can have a superscallar RISC. I just opened the David Patterson (The original Berkeley University RISC project Head and Sun founder shareholder) and John Hennessy (Stanford University´s Mips project head and MIPS shareholder) book and he give an example of the DLX processor (Didatic RISC processor) using superscallar techniques
IIRC the original Ditzel and Patterson [1980] work with the dificulties encountered by the high-level language architectures is that detailed the RISC idea.
IIRC some original RISC ideas come from some conversions with Seymour Cray. The Cray 1 had an incredible scallar performance and is one of the reasons it sold so well. Of course there is some IBM work with the 801 project but Cray had much more pratical experience.
RISC is about the smart design of ISA using the detailed analyses of high level language support.
The x86 ISA (Instruction Set Architecture) is CISC and has many flaws from the performance point of view.
Doing what? Database access? Just get any 128bits memory access modern RISC.
I understand
but it could be confusing for technonick.pcchen said:
Sure, it's a definition problem, but you can't avoid that problem making the assumption that RISC or CISC are about ISA and not about architecture, cause they are not. It was 20 years ago and it is now..about architecture and ISA. A RISC cpu is not a cpu with a minimum instrunction set, like a CISC cpu is not a cpu with a complex instruction set. Unfurtunately is not that simple. I bet no one would say the Rocwell 6502 was a RISC cpu
ciao,
Marco
Well, If we use the present x86 cores techniques and process to execute a new RISC ISA then my guess the RISC ISA will be faster than the old x86 like IA32.
The 6502 had a very small register file (part of the ISA), no instruction set optimization for high level language like C and can not be defined as RISC
The 6502 had a very small register file (part of the ISA), no instruction set optimization for high level language like C and can not be defined as RISC
Boy, oh boy, ANOTHER RISC vs CISC debate.
I think BenSkywalker put it best -paraphrasing here, that the debate is actually many debates and the many debates are spread across time, because the definition denotative and conatative keeps on changing with time. The first RISC cores weren't that RISCy the new CISC cores aren't that CISCy.
I believe modern x86 MPUs are defined to be CISC, this is because their front end -the layer that is exposed to us- is CISC.
Well that's enough stirring the pot from me.
I think BenSkywalker put it best -paraphrasing here, that the debate is actually many debates and the many debates are spread across time, because the definition denotative and conatative keeps on changing with time. The first RISC cores weren't that RISCy the new CISC cores aren't that CISCy.
I believe modern x86 MPUs are defined to be CISC, this is because their front end -the layer that is exposed to us- is CISC.
Well that's enough stirring the pot from me.
nAo said:Sure, it's a definition problem, but you can't avoid that problem making the assumption that RISC or CISC are about ISA and not about architecture, cause they are not. It was 20 years ago and it is now..about architecture and ISA. A RISC cpu is not a cpu with a minimum instrunction set, like a CISC cpu is not a cpu with a complex instruction set. Unfurtunately is not that simple. I bet no one would say the Rocwell 6502 was a RISC cpu
Well, at least to me a RISC ISA should have some properties: fixed length instructions, flat register file, limited addressing modes, and most instructions only access registers. 6502 does not share these properties.
The first RISC CPUs are designed as such to simplifying instruction decoding, pipelining, and eliminate microcodes. Therefore, ISA design is the most important difference between a RISC CPU and a CISC CPU. Architecture wise, there is no clear definition to define a "RISCy" architecture. What is a "RISCy" architecture? Pipelined? Many CISC CPUs without RISC core are pipelined. Parellel decoders or superscalar? The earliest RISC CPUs do not have such things.
So IMHO when talking about RISC CPUs, we are talking about the philosophy of their ISA, that's the most significant character of a RISC CPU.
pcchen said:
Maybe I was a bit unclear, I'm not saying 6502 is a RISC cpu, in fact I believe it's not. I was just being sarcastic.
Anyway, all those characteristics you listed are part of a PIII or K7 core.
In fact I don't think those features are RISC-like.
I'd put on top of the list orthogonality.
BTW..de gustibus non disputandum est
ciao,
Marco
nAo said:
Of course, but they are not visible to the software. x86 on a P3 or K7 still has variable length instructions and many addressing modes.
nAo said:
Some non-x86 CISC ISA are quite orthogonal, though. Furthermore, orthogonality is still an ISA feature, not an architectural feature, IMHO.
This "What constitues RISC vs CISC" thing reoccurs about every year. And there still is no better short explanation than John R. Mashey's now famous usenet post:
http://yarchive.net/comp/risc_definition.html
Cheers
http://yarchive.net/comp/risc_definition.html
Cheers
Part of the RISC ISA idea is have a large register file.
The x86-64 ISA try to be more risc like: www.x86-64.org
From the hammer presentation pdf file:
Some people speculate a improvment from 10% to 20% using the new ISA.
The x86-64 ISA try to be more risc like: www.x86-64.org
From the hammer presentation pdf file:
Some people speculate a improvment from 10% to 20% using the new ISA.
