Anyone know why the ps3 has 2 separate memory banks...

[ralexand]

They don't.

What are you saying here? It's fairly widely known that the RSX can access the XDR.

@Relazand: Anyway to partially address your original question, some theories are NVidia not being able to get their memory controller directly compatible with XDR, reduced cost of the GDDR modules, and the whole 'Cell limited to four devices' thing, which is untrue anyway, so...

But those are some of the ideas floating around for that.

Thanks for the info. I assume there is no performance hit if graphics data, textures etc. has to span across the 256mbs in the gpu memory.

 

[mckmas8808]

See thats the problem. You have mods that lead people like Teasy along thinking something that obviously false. Thanks for clearing these up xbdestroya and Guden Oden.
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[Teasy]

I made clear in my post why I thought each CELL could only address 256MB of ram. Nothing to do with jvd..

 

[jvd]

I made clear in my post why I thought each CELL could only address 256MB of ram. Nothing to do with jvd..

He is just trolling . I asked if it could that was all as I wasn't sure and just assumed it could .

 

[V3]

Then why use 2 seperate banks of memory? What am I missing?

More bandwidth. That's the reason you go with 2 pools.

When you connect 2 Cells together, they can address each other memory pool. With 2 pool, they can have more bandwidth, compare to one.

 

[ralexand]

Then why use 2 seperate banks of memory? What am I missing?

More bandwidth. That's the reason you go with 2 pools.

When you connect 2 Cells together, they can address each other memory pool. With 2 pool, they can have more bandwidth, compare to one.

The ps3 only has one cell.

 

[V3]

Then why use 2 seperate banks of memory? What am I missing?

More bandwidth. That's the reason you go with 2 pools.

When you connect 2 Cells together, they can address each other memory pool. With 2 pool, they can have more bandwidth, compare to one.

The ps3 only has one cell.

I was referring to Teasy comment about Cell not able to address more than 256 MB of memory. That's just not true.

The limit of 256 MB is currently due to how many memory chips Cell support at the moment and the size of memory for each chip. Not how much it can address.

 

[Npl]

The limit of 256 MB is currently due to how many memory chips Cell support at the moment and the size of memory for each chip. Not how much it can address.

The limit is just about the Cells local XDR-Ram( and its not 256 MB either as weve seen a Cell Mainboard with 8 or 16 XDR-Chips per Cell ). You could add a Memory-Controller( eg. DDR ) on the FlexIO Side and add as much as you want.

And its 2 Pools so that GPU and Cell can access a dedicated Pool for themselfes, thus not blocking each other.

 

[V3]

The limit is just about the Cells local XDR-Ram( and its not 256 MB either as weve seen a Cell Mainboard with 8 or 16 XDR-Chips per Cell ). You could add a Memory-Controller( eg. DDR ) on the FlexIO Side and add as much as you want.

And its 2 Pools so that GPU and Cell can access a dedicated Pool for themselfes, thus not blocking each other.

Yes, but I was talking about the speculation that was discuss sometimes ago. Because that was what I assumed Teasy was referring to.

 

[Nite_Hawk]

My guess is that the Cell processor likes the (supposed) low latencies of xdr memory, which is why they paired it up with XDR. I imagine that they probably were originally planning on doing something like an all XDR system, but found that they could get away with GDDR3 for the gpu without major performance losses and decided that the cost savings outweighed the advantages.

Who knows, maybe even Cell could get away with GDDR3, but they already had contracts in place with rambus and had to atleast put 256MB in.

Nite_Hawk

 

[ShootMyMonkey]

I made clear in my post why I thought each CELL could only address 256MB of ram.

There's nothing at all true about that. CELL has a full 64-bit address space. The limit is a fallacy created by assumptions around the fact that CELL simply has two XDR 32-bit controllers. With x16 (16-bit bus) XDR DRAM devices, you can only put 4 DRAMs to those two controllers (4 DRAMs * 512 Mbit = 256 MB). XDR DRAMs can scale all the way down to x1, so you can actually put 36 devices to a controller (32 data + 4 ECC). It just so happens that nobody is manufacturing x1 or even x8 XDR DRAMs, and besides which, keeping the number of DRAMs down does indeed enable you to make the unit small and compact. If there were 1 Gbit XDR DRAMs in mass production, then they'd use them if only to show up with the biggest specs and stick their tongues out at MS.

The access to opposite RAMs is not direct. There's the FlexIO bus connecting CPU<-->GPU. The CPU can queue requests to the GPU's memory controller giving its device ID, so that whatever it requests are directly transferred. The GPU does likewise. It's not a direct link, so there's added latency, all right, but from the software standpoint, it's supposedly transparent (the OS direct maps all the memories in the system to specific ranges in virtual memory space -- at least, that's what I got from the presentation slides).

 

[London Geezer]

There's nothing at all true about that. CELL has a full 64-bit address space. The limit is a fallacy created by assumptions around the fact that CELL simply has two XDR 32-bit controllers. With x16 (16-bit bus) XDR DRAM devices, you can only put 4 DRAMs to those two controllers (4 DRAMs * 512 Mbit = 256 MB). XDR DRAMs can scale all the way down to x1, so you can actually put 36 devices to a controller (32 data + 4 ECC). It just so happens that nobody is manufacturing x1 or even x8 XDR DRAMs, and besides which, keeping the number of DRAMs down does indeed enable you to make the unit small and compact. If there were 1 Gbit XDR DRAMs in mass production, then they'd use them if only to show up with the biggest specs and stick their tongues out at MS.

The access to opposite RAMs is not direct. There's the FlexIO bus connecting CPU<-->GPU. The CPU can queue requests to the GPU's memory controller giving its device ID, so that whatever it requests are directly transferred. The GPU does likewise. It's not a direct link, so there's added latency, all right, but from the software standpoint, it's supposedly transparent (the OS direct maps all the memories in the system to specific ranges in virtual memory space -- at least, that's what I got from the presentation slides).

In his defence, he did say:

I made clear in my post why I thought each CELL could only address 256MB of ram.

and not

I made clear in my post why each CELL can only address 256MB of ram.

 

[marconelly!]

My guess is that the Cell processor likes the (supposed) low latencies of xdr memory, which is why they paired it up with XDR. I imagine that they probably were originally planning on doing something like an all XDR system, but found that they could get away with GDDR3 for the gpu without major performance losses and decided that the cost savings outweighed the advantages.

That would be my guess too, based on everything I've read here.
Also, much higher (doubled essentially) total bandwidth is likely reason.

 

[Nite_Hawk]

My guess is that the Cell processor likes the (supposed) low latencies of xdr memory, which is why they paired it up with XDR. I imagine that they probably were originally planning on doing something like an all XDR system, but found that they could get away with GDDR3 for the gpu without major performance losses and decided that the cost savings outweighed the advantages.

That would be my guess too, based on everything I've read here.
Also, much higher (doubled essentially) total bandwidth is likely reason.

doubling the amount of XDR would have doubled the throughput too though. I imagine in the end the cost savings of going with GDDR3 and XDR rather than just XDR probably outweighed any performance gain they would have gotten by using only XDR.

Nite_Hawk

 

[Acert93]

Then why use 2 seperate banks of memory? What am I missing?

1. Cost. XDR is more expensive. Its main benefit is low latency which CELL requires but the RSX can do without for the most part.

2. Not knowing how much time RSX was in development for the PS3, there is always a chance they did not have the time to create an XDR memory interface.

 

[gurgi]

I'm probably going to look dumb, but maybe 2 pools of ram with different pipes is cheaper than a larger pool at twice the bandwidth?