Toshiba, Sony take trench capacitors to 90-nm node
By Yoshiko Hara
EE Times
January 17, 2003 (12:48 p.m. EST)
Archives
TOKYO — Toshiba Corp. said it is leveraging its deep-trench-capacitor DRAM structure, which it has championed as a process driver since the 0.25-micron generation, to migrate its system-on-chip devices to the 90-nanometer and 65-nm process nodes ahead of its competitors.
Process development partner Sony Corp., meanwhile, is formulating plans for production at the two next-generation nodes and said it will migrate to the trench-capacitor structure from a stacked-capacitor architecture developed with Fujitsu.
Toshiba has been shipping engineering samples of 90-nm embedded-DRAM devices since November and expects to begin volume production in March with a startup capacity of 1 million units per month. Small-scale production of devices at the 65-nm node is expected a year later, in March 2004.
The processes have been in development under a three-year joint R&D project launched with Sony in April 2001. Engineers from both companies have been working at Toshiba's research center in Shinsugita, Yokohama, near Tokyo.
Strange bedfellows
Sitting next to a competitor's engineers to discuss technology development and R&D cost sharing has been "quite a new experience for Toshiba engineers," said Tatsuo Noguchi, senior manager of the advanced CMOS technology group at Toshiba Semiconductor Co.
"Sony has been working with partners since the 0.18 micron generation. For 90 and 65 nm, we collaborated with Toshiba," said Naoaki Nagashima, general manager of the integration technology department at Sony Semiconductor Network Co.
Total investment by the two companies is expected to be about 15 billion yen (about $127 million) for the three-year project. The first phase, targeting the 90nm-node, was completed in September. Toshiba immediately began risk (test) production at its Oita fab.
Work on the 65-nm process started last April and is scheduled for completion by March 2004. Toshiba intends to begin 65-nm production immediately upon completion of the joint R&D work. A 300-mm fab to be built at the Oita site is slated to begin turning out devices in the 65-nm process next year.
Sony has made no firm decisions on when and where to begin production of devices using the CMOS4 and CMOS5 (90- and 65-nm) processes, according to Nagashima. One decision that has been made however, is that Sony will adopt the processes jointly developed with Toshiba and will switch to deep-trench-type DRAM for its embedded-DRAM devices, dropping the stacked-capacitor structure co-developed with Fujitsu.
"Toshiba's Oita fab is ready for volume production of CMOS4 process devices, which we believe [puts us in the lead at the 90-nm node]," said Masaka-zu Kakumu, general manager of Toshiba Semi's advanced logic technology department.
The company attributes its advantage in embedded-DRAM devices to the deep-trench capacitor. When trench-capacitor DRAMs are integrated onto system-on-chip devices, the DRAM process is completed before the logic device process. In stacked-capacitor-structure embedded DRAM, by contrast, the DRAM cell is built on the metal wiring layer, and the high-temperature process used for the DRAM cells can deteriorate the transistors underneath that layer, Toshiba claims.
The CMOS4 and CMOS5 processes continue a practice Toshiba has had in place since the 0.25-micron generation, when trench-capacitor DRAM became the linchpin technology for process advances at the company. According to Toshiba, the strategy has given it a leg up at the 130-nm node, where it claims to be the only company to date to have undertaken true mass production of embedded DRAM. For its 90-nm process, device yields for 32-Mbit embedded DRAM have reached the volume-production level, according to Kakumu.
At Toshiba America, sales are under way for the TC300 family, based on the CMOS4. The devices feature up to 11 layers of copper metal interconnect with low-k dielectric and logic densities of up to 400,000 gates/mm2.
For the 90-nm node, Artisan Components will provide libraries for Toshiba's devices, with availability expected this summer. Toshiba offers proprietary libraries but expects Artisan's CMOS4 environment to appeal to customers of foundries, such as Taiwan Semiconductor Manufacturing Co., to which Artisan will provide its design platform and libraries. Foundry customers can move to Toshiba's process using the design interface provided by Artisan.
Toshiba added ArF lithography and low-k dielectric facilities to the clean room of its Oita fab for CMOS4 fabrication. The CMOS4 line now has an 8-inch wafer capacity of 27,500 a month. Toshiba and Oita TS Semiconductor Co. Ltd. (OT-SS), a joint-venture fab with Sony Computer Entertainment Inc., share the fab's capacity.
CMOS5
Sony and Toshiba presented the basic technologies for their 65-nm process in December at the International Electron Devices Meeting. "We have reached a level where we can show the performance of the transistor fabricated on the process. On this level, we are sure that we can begin production in March 2004," said Seiji Yamada, chief specialist at Toshiba Semi's advanced CMOS technology group.
Fabricated with 193-nm lithography and phase-shift masks, the transistor is reported to hit switching speeds of 0.72 picosecond for an n-MOSFET and 1.41 ps for a p-MOSFET at 0.85 volt. The embedded DRAM cell measures 0.11 micron2, allowing a 256-Mbit DRAM to be housed on-chip with logic. The process' embedded SRAM has a cell size of 0.6 micron2.
The new technology enables a 180-nm pitch, a 75 percent shrink from the 90-nm generation. The process employs a low-k dielectric material with a targeted effective interlayer dielectric constant of around 2.7.
Toshiba intends to prepare up to 13 usable metal layers for CMOS5 to provide design leeway for customers seeking to use existing IP with multiple layers on the 65-nm platform.
) as you base your approach on basic and uniform bulding blocks which you basically repeat over and over and that can svae you costs as you do not need several heavily diversified manufacturing lines... you might use the same one...