AMD: Zen 4, Speculation, Rumours and Discussion

hoom

hoom

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Since nobody else did it: Have at it.

AMD Computex 2022 keynote

5nm
1 or 2* 8-core chiplets
1MB L2/core
Designed for higher clocks & demonstrated a 16 core pre-production chip hitting 5.520Ghz ingame
Claiming 15% better single thread
6nm IO die with integrated graphics, DDR5 & PCIE5

AM5
LGA 1718 pin
Up to 170W TDP
Compatible with AM4 coolers
Dual channel DDR5
24* PCIE5 'for storage & graphics'
Up to 14* SuperSpeed USB 20Gbps/USB-C
Supports Wifi 6E
Up to 4* HDMI 2.1/DisplayPort2
New power control stuff
3 chipset levels:
X670E (PCIE 5 everywhere, most OC stuff)
X670 (PCIE 5 only on Graphics & Storage)
B650 (only PCIE 5 on storage & less overclocking)
--------------------------

I think most of this has been rumoured already?
Actually stating they've designed for over 5Ghz is a surprise to me & doing it same time as doubling L2 from 512KB/core is impressive.
Didn't actually claim any particular clock for release parts or say anything about TDPs.
If they've managed that kind of clock increase with same TDPs as Zen3 then super impressive, I suspect there'll be a bit of TDP creep though.
15% single thread increase is explicitly including and may be largely in the increased clock rate.
No mention of X3D versions.
Dropping to 6nm on IO die already, I never really bought that they would keep using significantly bigger process like they started out with, putting an IGP in there pretty much forces them to go for smaller process.
Presumably the IGP is gonna just be a waste of die space that you turn off in BIOS unless you're building a basic office PC/when your GPU dies until you can find a working old spare/new one arrives, will mostly just function as extra cooling area.
AM5 compatible with AM4 coolers is good.
Was AM4 20 lanes by same metric or 24? I think B550 has 20? So that means 2*4-lane PCIE5 for NVME?
Does Wifi6e actually require on-chip stuff? Won't that just be a PCIE/whatever standard IO lane thing?

Don't like the sound of this intel-style feature levelling in the chipsets at all :-|
 
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I still have my original board from when the 1700x came out. Been waiting for AM5 socket to hit. Zen 4 sounds to be a beast. The 16 core chip at 5ghz would be a huge improvement from my 3700. PCIE-5 and ddr 5 lets me catch up in one swift upgrade.
The IPC performance is also really nice if it holds true.
 
hoom said:
Was AM4 20 lanes by same metric or 24? I think B550 has 20? So that means 2*4-lane PCIE5 for NVME?
Click to expand...

IIRC Zen 3 has 24 lanes but 4 of them are used for connection with the chipset so only 20 lanes are user usable.
Not sure what AMD means on Zen 4 though, but "for storage and graphics" seems to suggest that they are all user usable.
 
hoom said:
Presumably the IGP is gonna just be a waste of die space that you turn off in BIOS unless you're building a basic office PC/when your GPU dies until you can find a working old spare/new one arrives, will mostly just function as extra cooling area.
Click to expand...

It could also be that they may use that for MS's Direct Storage as they mentioned something about their Direct Storage support to be more than what people might expect. For GPU based decompression that means it could be done directly on the SOC and the data wouldn't necessarily have to travel to the GPU. Perhaps a direct benefit for data that would be used by the GPU anyway, but would be a potential benefit if the data needs to also populate system memory (either the GPU doesn't need it or they need it in system memory as well as GPU memory).

Also one from LTT with their take on it.


Just some interesting takes from their POV. For example, they attribute the 15% IPC increase to the doubling of the L2 cache to 1 MB.

Regards,
SB
 
Yeah if the I/O die integrated graphics can do double-duty as offboarding a bunch of the decoding/encoding stuff that was being done by a dedicated unit on the CCX chiplet they might be able to free up some CCX die-space/TDP budget?

Lisa Su said the 15% is per-thread not IPC & includes the clock boost.
Certainly the extra L2 should help in a bunch of cases as well but if they're counting the clock as 5.5Ghz vs 4.9 (not a given) thats 12% increase purely in clock.
 
hoom said:
Lisa Su said the 15% is per-thread not IPC & includes the clock boost.
Certainly the extra L2 should help in a bunch of cases as well but if they're counting the clock as 5.5Ghz vs 4.9 (not a given) thats 12% increase purely in clock.
Click to expand...

Yeah, seems like a "tock" to me. Few, if any, microarchitetural advances with all the performance gains coming from process improvements (higher clocks, larger caches) and the DDR5 memory interface.

Cheers
 
So here is some stuff about the chipsets: https://www.techpowerup.com/295394/amd-zen-4-socket-am5-explained-pcie-lanes-chipsets-connectivity
(Not sure to what extent this is confirmed vs rumor?)

Apparently they've got a single new 'Promontory 21' chip for the 3 levels, B650 is 1 chip, the others are 2 of them daisy-chained with a 4* PCIE4 link
It is 4 more PCIE lanes off CPU: 16* for GPU & 2* 4* for M.2 and 4* to chipset = 28 lanes total vs B550 had 24 lanes total by same standard.

Each Promontory 21 has 16* PCIE lanes: 4* PCIE4 to CPU, 4* PCIE3/SATA and another 8* PCIE4 for M.2/other IO but for the two-chip chipsets 4 of these on 1st chip are used for the link to 2nd chip -> 4* lanes for this chip = 12* available between the 2 chips.
4* PCIE 4 from the cpu to chipset even on X670E where the 2nd chip also needs to get to the CPU through it.

I made perhaps a mistake of looking at AMD Reddit 😅
Some very vocal complaints about that last bit along the lines: 'the chipset link is gimped -> everything connected to the chipset will be useless, especially on the 2nd chipset'
To an extent I can understand disappointment with it being only a PCIE 4 link when they're going to PCIE 5 for GPU/M.2 on the CPU itself. You potentially have 12* PCIE4 lanes of bandwidth contending for only 4* PCIE4 bandwidth through to the CPU & thats without including USB/SATA traffic.
On the other hand I feel like very few users would actually have a use case where they will even come close to saturating that 4* PCIE4 link except maybe brief peak loads.

I dunno, maybe other people really do actually have that kind of use case :?:


Some complaints point to the Intel Z690 chipset as a better solution since it has the 8* DMI4 CPU -> Chipset link with 16GB/s vs AMDs 4* PCIE4 8GB/s.
But an examination of the chipset diagram in the link (appears to be official Intel so I'm assuming its correct? & assuming my GB/s numbers are correct?) shows this to be bullshit.
Z690 has only PCIE5 direct to CPU for the GPU and all M.2 traffic will have to cross that 16GB/s DMI link (2* PCIE4 M.2s = 16GB/s = maxed), while AMD has 32GB/s (2* 4* PCIE5) M.2 bandwidth direct to CPU.
Edit: I was misreading the diagram 😳 Z690 has 1* 4* PCIE4 direct to CPU, see next 2 posts


Additionally since Computex there has been clarification on a few things (from Hallock I believe so take with a marketing/PR size handful of salt):
PCIE4/5 levels - the B650 chipset itself remains capable of PCIE5 but the PCB/trace min specs are set to PCIE4 to allow for cheaper SKUs because PCIE5 specs are really tight.
I interpret that as meaning a B650 mobo built to same standard as the X670 boards would be able to do PCIE5?

Overclocking - apparently B650 will still offer normal overclocking features, just the lower min-spec = less potential. I hope this is all they meant not stupid Intel style hard price-point feature limits.

TDP - https://www.tomshardware.com/news/a...zen-7000-power-specs-230w-peak-power-170w-tdp
AMD Socket AM5 supports up to a 170W TDP with a PPT up to 230W.
Click to expand...
AM4 had 142W PPT max.
Its not in the linked article & I can't seem to find one but I thought I saw the actual Zen4 CPU SKUs will be maxing 125W TDP.

IPC - definitely salt required but hints there is actually significant IPC stuff they're just not talking about yet.
 
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hoom said:
Some complaints point to the Intel Z690 chipset as a better solution since it has the 8* DMI4 CPU -> Chipset link with 16GB/s vs AMDs 4* PCIE4 8GB/s.
But an examination of the chipset diagram in the link (appears to be official Intel so I'm assuming its correct? & assuming my GB/s numbers are correct?) shows this to be bullshit.
Z690 has only PCIE5 direct to CPU for the GPU and all M.2 traffic will have to cross that 16GB/s DMI link (2* PCIE4 M.2s = 16GB/s = maxed), while AMD has 32GB/s (2* 4* PCIE5) M.2 bandwidth direct to CPU.
Click to expand...

Alderlake has x16 PCIe 5.0 + x4 PCIe 4.0 (m.2) + x8 DMI 4.0 (to the chipset). B660 and H610 chipsets themselves however only support x4 DMI 4.0. PCie/DMI 4.0 is a minimum requirement for all motherboards regardless of chipset. Alderlake regardless of chipset does not have PCIe 5.0 to any m.2 slots.

I'm not sure what diagram you are referring to but it shows the x4 PCIe 4.0 link off the CPU on this one - https://download.intel.com/newsroom/2021/client-computing/z690-chipset-brief.pdf
 
Right you are, I was expecting the M.2 link on the CPU to have its own block so I managed to completely skip the bit where its stated in the same block as the 16* PCIE5 to GPU :oops:

Diagram from the article https://www.techpowerup.com/img/Uqrbfd5ifZSQZgBh.jpg looks to be same as in that pdf.

It is only a single 4* PCIE4 link though
So for a situation with 3* PCIE4 M.2 drives they both have equal bandwidth.

Still a theoretical minor advantage to AMD because Intels 2nd & 3rd have to contend with other IO while only AMDs 3rd has to contend with other IO & potential significant AMD advantage with available upgrade to 2* PCIE5 with full dedicated bandwidth.
 
This is why I don't like the the tendency to frame things towards AMD/Intel (or Nvidia) comparisons. Alderlake doesn't even really have support PCIe 5.0 m.2 storage, so I'm not even sure why it's a useful direct comparison. It can serve as a illustrative comparison of having faster chipset link speeds, but the overall platforms aren't really competitors in that respect.

One of the selling points for some people with AMD's AM4 and soon to be AM5 platform is that it kind of straddles into what you consider as "HEDT."

AM5 with Zen 4 and x670e on paper has a lot of connectivity support but a weak link (hohoho...) with the PCIe 4.0 link off the x670e chipset in practice limits those looking to push into that high end connectivity niche but don't want to fully move up to the next platform tier which has additional complications/issues/costs/etc. associated with doing so. The issue isn't that those people will now be forced to consider Intel's mainstream platform (which is even more mainstream on the connectivity side).

At least that is my understanding of some of the situation as I'm not in that target market, as until we maybe get some in depth tests of direct storage showing otherwise even PCIe 4.0 over 3.0 SSDs to me in practical terms would be niche.
 
It should be noted that at the last Microsoft all hands meeting this past Wed the steam deck was brought up and the question was about seeing more amd chips inside of the surface line up. The answer was a little more than the generic can't answer that. They specifically said that would mean discussing future products and that the surface line was not meant to be a graphical beast.

So perhaps AMD has some Zen 4 wins inside of Microsoft products ?
 
eastmen said:
It should be noted that at the last Microsoft all hands meeting this past Wed the steam deck was brought up and the question was about seeing more amd chips inside of the surface line up. The answer was a little more than the generic can't answer that. They specifically said that would mean discussing future products and that the surface line was not meant to be a graphical beast.

So perhaps AMD has some Zen 4 wins inside of Microsoft products ?
Click to expand...
Would love to see a Phoenix Point APU in a Surface laptop.
 
www.guru3d.com

AMD confirms next-generation Zen 5 CPU microarchitecture, Zen 4 just 8–10% faster IPC

It's a bit early and ambitious but in its Financial Analyst Day 2022 presentation AMD is creating some waves with the mention of Zen 5 CPU microarchitecture....
www.guru3d.com www.guru3d.com

Built on 5nm technology, the slide above shows that instructions per clock (IPC) have improved by 8–10% over the current Zen 3. AMD says that higher frequencies boost single-thread performance by 15%. Zen4 will also introduce an extra Vcache.
Click to expand...
index.php
 
Gubbi said:
Yeah, seems like a "tock" to me. Few, if any, microarchitetural advances with all the performance gains coming from process improvements (higher clocks, larger caches) and the DDR5 memory interface.

Cheers
Click to expand...
That's a 'tick' actually, but then as far as Intel is concerned the clock got broken several intervals ago (maybe it was a baroque clock :mrgreen:).
 
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Apparently because of the change to LGA the package is thinner so since they promised heatspreader compatibility they had to make a thicker heatspreader.
 
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