AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

I find that hard to believe with the the amount of the shader array has changed. But then agian has it change to the degree it has based on what they have shown so far or just a modification, not sure.......need more info but as it stands, looks like they have made quite a bit of changes in pretty low level areas.

 

Interesting, didn't think about it that way!

 

Did the 1080 and Titan X also have all their vents taped shut?

It's an engineering sample, we can't tell much about Vega yet.

Regards,
SB

 

One of the few things we can tell is its minimum performance. Even tho is AMD chose this games was for specific reasons and not randomly.

 

The 280X is even (very slightly) ahead of the 780 in 3840x2160.

 

Theres one thing with Doom who was trouble me a little bit, They was using Vulkan, but so Vulkan need a few optimisations for specific gpu's. Is the developpers have allready setup specific path for Vega ? So far of the launch, we can only see the performance increase anyway. ( but ofc i speculate there )

 

Pretty impressive actually...although I think games are umpleyable with those res on those cards

 

I dont know AMDs relation with valve but something like that will require AMD to disclose very deep parts of its architecture very early to many people.

 

It could still be 64 lanes though, given that FMA and MAD are usually counted as two ops.

 

But that's also the case for the old CUs, so it can't explain the doubling of ops in the slide.

 

How about dropping the 4-cycle cadence for a new dual-issue scheduling scheme for SIMD instructions?

 

Or it means literally four stacks.

But the point being touted for the memory controller is virtual address space and fine-grained data movement, not a unified physical pool. The bullet point being taken off your list (hardware page management support) kinda reflects this.

Seems like they are going after Nvidia's path in relying on the address translation hierarchy for the de facto cache management. It would be interesting to see how it fits into their HSA-influenced ROCm stack.

Since it specifically says xGMI for peer-to-peer link, what is being claimed is more likely dedicated links for inter-GPU traffic like NVLink.

 

Unless the die Raja was holding isn't Vega 10, there won't be two dice on an interposer. Vega 11 would be the only case where two on an interposer might be practical. Vega 10 at 500mm2+ along with the RAM rules that out. That package would be enormous. That would be a traditional dual card which should be able to share data and a density option for enterprise.

No reason they couldn't build upon those instructions either. 4 operands for FMA4, if they added that, definitely makes the packed math easier.

 

I know internal slides are required by law to look like garbage, but these don't really inspire confidence.

 

None of the Vega products quite match features attributed to Greenland via Linkedin or the HPC APU rumors. The supposed lead chip has 1/2 rate DPFP, with the "APU" using it having PCIe 3.0. I suppose there could be a wrinkle related to the CPU component that could explain that, although why AMD would hold back on double-precision for compute products if it were there is unclear.

 

I guess we always assumed Zen and Vega would be separate chips for the APU. Given their mesh, really big APUs might make sense. There could be a Zen APU with a bunch of half rate DP Vega cores that wouldn't technically be a Vega variant. No reason it couldn't get turned into a discrete C/GPU. Zen cores might actually be interesting in a FP64 scientific environment with the prediction. Definitely makes virtualization easier when sharing a supercomputer.

If Vega 11 is the consumer variant, I can't imagine FP64 was added there. Vega 20 in theory has FP64, but is a ways off.

 

Im really not quite sure about the " 2018-2019" roadmap. Why keep Vega 10 if you have Vega20 on 7nm. ( who seems only add DP and GMI ) ? Ofc without having the context of thoses internal slides ( if really sorted by AMD ) its a bit hard to know if the roadmap is really accurate.

 

That would seemingly make a discrete Vega with 1/2 rate DPFP easier, rather than pushing the specs of the supposed lead chip whose name showed up early in driver strings to another node.