AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Yes, that is what AMD is saying.
-Navi = RDNA = Games
-Vega = CGN = Compute


Navi probably doesn't spend much on FP64, it is not needed in gaming.
 
Being gaming-centric, Navi /RDNA might be offering lower compute throughput per watt and/or die area than Vega / GCN 5 (at similar process nodes, of course).

AMD seems to be hinting at forking their gaming and compute architectures.
We'd have to wait and see what changes from Navi would be relevant to the compute space. There were compute and HSA-related changes for it, and an updated cache hierarchy would seem like a good idea for GCN, since the cache subsystem was one of the least evolved parts of the architecture since it was introduced.
 
We'd have to wait and see what changes from Navi would be relevant to the compute space. There were compute and HSA-related changes for it, and an updated cache hierarchy would seem like a good idea for GCN, since the cache subsystem was one of the least evolved parts of the architecture since it was introduced.

What if Navi's RDNA architecture is a really forward design from GCN, with a much more smarter & robust frontend..? All designed to reduce latencies and improve IPC.

If Navi is truly what Dr Su says it is, designed specifically for gaming....
..then how would you all here, design a new engine, using the best pieces of/from GCN & other modern designs (PlayStation/Xbox)..? Ponder how much collective wisdom is here and how we would design a game specific GPU.... -VS- how AMD & Dr Su did it, after Raj...

She said Navi is the future of gaming.


What if some of the fine wine is being opened..? And this keynote was a sniff..?
 
What if Navi's RDNA architecture is a really forward design from GCN, with a much more smarter & robust frontend..? All designed to reduce latencies and improve IPC.
I think there is a mixture of new features and also a lot of overlap with prior GCN GPUs.
AMD is free to declare Navi to be a new architecture and provide the details on what is new and different. Depending on how large the difference is, and in what areas, I think the distinction can appear stronger the more evidence is provided and the more AMD clarifies its meaning.

If Navi is truly what Dr Su says it is, designed specifically for gaming....
..then how would you all here, design a new engine, using the best pieces of/from GCN & other modern designs (PlayStation/Xbox)..? Ponder how much collective wisdom is here and how we would design a game specific GPU.... -VS- how AMD & Dr Su did it, after Raj...
There are some features documented so far that would work well for other workloads, and some like HSA-related changes that gaming hasn't cared for.

She said Navi is the future of gaming.
At a minimum, counting the PS5 and possibly the next Xbox, that's ~6 years at least. A mid-gen update like the Xbox X and PS4 Pro could extend Navi's market relevance to 8-10.
The PS4 is likely to persist as a product by dint of its success a significant way into the next gen as a legacy/value line.
 
Splitting gaming and compute lines makes sense. The compute baggage is weighty.

AMD emphasising Vega/GCN is not going away is understandable. Hawaii-based cards had ~5 years life time, right?
 
I think there is a mixture of new features and also a lot of overlap with prior GCN GPUs.
AMD is free to declare Navi to be a new architecture and provide the details on what is new and different. Depending on how large the difference is, and in what areas, I think the distinction can appear stronger the more evidence is provided and the more AMD clarifies its meaning.


There are some features documented so far that would work well for other workloads, and some like HSA-related changes that gaming hasn't cared for.


At a minimum, counting the PS5 and possibly the next Xbox, that's ~6 years at least. A mid-gen update like the Xbox X and PS4 Pro could extend Navi's market relevance to 8-10.
The PS4 is likely to persist as a product by dint of its success a significant way into the next gen as a legacy/value line.


Thank you for your response.

This is where in her keynote she gets passionate.
1558924659877568230923666131846.jpg
 
Found this, the 4x 2-wide VLIW looks similar to what RDNA could be, also the changes in the Registerfile looks similar.
The optimization relating context-switches seem very smart.

But the Do$ and some other stuff of the AMD patent is not there.

https://ce-publications.et.tudelft...._in_a_multiported_vliw_register_file_impl.pdf

^^
"In this paper, we propose to re-purpose these unused BRAM resourcestoadditionallysupportmultiplecontextsnexttoearliermentioned modes. In this manner, the 8-issue, 4-issue, and 2issue cores have access to 4, 2, and 1 contexts, respectively."
 
Splitting gaming and compute lines makes sense. The compute baggage is weighty.

AMD emphasising Vega/GCN is not going away is understandable. Hawaii-based cards had ~5 years life time, right?

Hell, anyone who bought a Radeon 7970 in late 2011 is still getting a relatively great gaming experience at 1080p, if it's still working. I had an R9 270 (respun 7870) from late 2014 to early 2018. Yeah it had it's limitations, but for the most part I never felt like a good 1080p experience was out of reach, save for PUBG. Furthermore, the Radeon 7750 in my wife's computer from late 2013 to mid 2017 was moreso limited by it's 1 GB GDDR5 than it's 880 GFLOPS.

Visually, the next console generation is already once again being defined in PC graphics hardware a year prior to earliest expected arrival. And the rumor is that the lower end nextBox SKU will be in the 4 to 6 TFLOP range. Could give alot of old high end AMD GPUs a new lease on life if VRAM isn't an issue.
 
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The link speed is lowered a bit to 21 Gbps from the Instinct line's 25 Gbps, perhaps for power savings.
And at least the PCB for the Duo seems to be completely custom for the Mac Pro. The card is powered by a secondary slot placed behind the regular PCIe 3.0 x16.




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They also added a Thunderbolt 3 controller.
It might be another PCIe 3.0 x16 but next to a larger ground "finger" (for larger currents), to compensate the fact that Skylake SP doesn't support PCIe 4.0, otherwise feeding 29TFLOPs worth of GPU could be a bottleneck.
This way they'd have up to 28 PCIe 3.0 lanes for the GPUs, plus 4 lanes for Thunderbolt.

Thing is Skylake SP only has 48 PCIe lanes, so the dual Duo card configuration will put at most 20 PCIe 3.0 lanes for each Vega 20 chip (48 / 2 = 24 -> 20 for GPU, 4 for TB3.0). And this is assuming all storage is connecting through the southbridge which might not be.



In the end, I think this is a bit of a lost opportunity for apple to adopt Rome as it would be much better option for expandability than the rather old Skylake SP. I just don't know if AMD would be ready to provide the CPUs on time nor how much use apple gives to AVX-512.
 
Does this mean we will see a Navi x2 for gaming? (Is that what big navi is?)
Doubtful. In the gaming space it's just a lot more difficult to support multi GPU, especially with DX12/Vulkan mgpu now dependent on the game dev to support.
 
Thing is Skylake SP only has 48 PCIe lanes, so the dual Duo card configuration will put at most 20 PCIe 3.0 lanes for each Vega 20 chip (48 / 2 = 24 -> 20 for GPU, 4 for TB3.0). And this is assuming all storage is connecting through the southbridge which might not be.
Very unlikely. IF means they effectively have a "free" PCIe switch on that card, as the PCIe topology extends across IF as if it was just a simple switch. I don't know how many lanes of IF / PCIe 3.0 / 4.0 Vega actually has in hardware, but I suppose we can safely assume that on top of all the IF lanes, there is a total of at least 16 unconnected PCIe 3.0 lanes on that PCB. So if there is TB controller on that card, don't assume it's actually wired directly to the socket, it's pretty certainly daisy-chained to one of the GPUs. Maybe it's not connected via PCIe on PCB either, but the thunderbolt chip

Since IF nodes effectively behaves same as an PCIe switch, it's pretty much safe to assume that both Vega 20 chips are also only connected to a single PCIe 3.0 16x port together. I even doubt there is any real difference in performance between them connecting in a split 8+8 or a pure 16 daisychain configuration.

These connectors on top of the GPU also render your assumptions about "20 lanes per GPU" somewhat moot. That's pretty obviously intended for a ring topology of 4 Vega 20 chips spread over 2 PCBs, with PCIe 3.0 16x on the socket each.

The two 10 Gbit Ethernet interfaces, on top of the NVMe slots also indicates that IO is certainly not handled entirely by the south bridge either. A raid of two NVMe SSDs is sufficient to top out the DMI 3.0 link to the Southbridge, if you actually were to place them there. So I'm pretty certain there is 1x4 or 2x4 lanes reserved directly from the CPU for storage, plus probably a couple of "spare" electrical 8x slots not used by MPX for customers who need extra cards other than GPUs.
 
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