AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

We will soon find out if current Vega is borked or not(Adrenalin). I'm guessing there is no issue and it's exactly like Raja said. Software is hard on this one. The tell is that a shot of adrenaline makes you stronger. Why call it that if perf isn't going up? If there was a hardware issue they've had plenty of time for a respin. AMD was already planning a Vega refresh on the 12nm node before this hard forum poster chimed in. It might be hard to separate a respin + node shrink to understand where a supposed issue was. He will claim sage even though things have been in motion to further boost Vega's perf.
 
Ryan Smith said:
At this point can anyone name what it is they'd like to see? It seems like this whole thing has transcended into a meme.
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- FP16 exposed in OpenCL and not only DX. And when exposed, not only for compute shaders but pixel shaders too (maybe new drivers have fixed that, I didn't check tbh)

-"automated" Primitive shaders / discard thing ?

-And, I'm not sure what is the state of the Draw Space Binning Rasterizer ?

In short, all the things not making Vega "just" an OC Fiji with HBCC and a different communication with the L2 cache.
 
Rootax said:
- FP16 exposed in OpenCL and not only DX. And when exposed, not only for compute shaders but pixel shaders too (maybe new drivers have fixed that, I didn't check tbh)

-"automated" Primitive shaders / discard thing ?

-And, I'm not sure what is the state of the Draw Space Binning Rasterizer ?

In short, all the things not making Vega "just" an OC Fiji with HBCC and a different communication with the L2 cache.
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DBSR we know is in a working state, but we don't know how widely it's being applied. AMD said they have it enabled for the 'energy' spec perfview bench.
 
Rootax said:
I think the message is "the hardware is fucked up / broken, but the blame was on the software team".

If we never see thoses "disabled functions" on original Vega, I'll be kind of pissed...
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Found a video summary of that thread.

Ryan Smith said:
At this point can anyone name what it is they'd like to see? It seems like this whole thing has transcended into a meme.
Click to expand...
Memes are modern communication and marketing in 140 characters or less. Strip out all the substance and understanding you have a meme. Or the discussion linked in the video above.

Considering the potential scope of a compiler bug that only recently got fixed, coincidentally discovered shortly before they announced Adrenaline, it's a bit surprising AMD had anything working reliably. At the very least it would be nice to see some official confirmation on the state of DSBR, primitive shaders, and SM6.x.
 
Rootax said:
- FP16 exposed in OpenCL and not only DX. And when exposed, not only for compute shaders but pixel shaders too (maybe new drivers have fixed that, I didn't check tbh)
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OpenCL Pixel Shaders? I understand that these missing features are legion, but I don't think that a rewrite of the OpenCL spec was ever advertised...
 
Rootax said:
I think the message is "the hardware is fucked up / broken, but the blame was on the software team".

If we never see thoses "disabled functions" on original Vega, I'll be kind of pissed...
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I think the context of some of the disabled functions is that AMD hasn't mentioned them. In that case how would it appear differently to an outside observer whether a refresh added new features versus fixed disabled ones?

The leaked slide about Vega 20 indicated items such as ECC and higher 64-bit throughput, but that was ostensibly a process adjustment and rebuild rather than a respin.

Ryan Smith said:
At this point can anyone name what it is they'd like to see? It seems like this whole thing has transcended into a meme.
Click to expand...
Don't know about what I'd like to see, necessarily.

If we were to go by the older leaked slides that had Greenland as the code name for the lead GPU of Vega's generation, and as part of the various HPC APU slides, and in driver strings for Vega 10:
Vega 10 would seemingly have a few things that might be hiding internally: on-die ECC, (memory ECC is apparently now showing up in Linux changes), higher FP64 throughput, xGMI (or GMI links, per other slide).

Possibly not Vega's fault, but 2.0 Gbps HBM2 would be something due for a refresh. HBM2 is also allegedly operating above the top end of the spec in terms of voltage for Vega, though whose fault that is isn't clear.

Vega's ISA doc has a few primitive shader and other front-end related changes, and that may mean there are currently undisclosed modes or opcodes with further features, given the sparseness of the documentation.

While we're at it, the full set of power-saving, DVFS, and other features AMD has announced should be reviewed. Some of the disclosed features like boot-time voltage adjustment or dynamic voltage adjustment were disclosed for Carrizo, Fiji, Polaris, and others that were allegedly not used in the products.

More pie in the sky would be items that AMD has discussed over the years without results--from better methods of cache coherence to ways of establishing more robust memory consistency (different cache hierarchy or utilization of cache ways, time-based consistency, different synchronization, etc.), better divergence handling (if not the wildly bandied about variable SIMD patents, more modest instruction support to allow divergence without deadlocks).
 
3dilettante said:
The leaked slide about Vega 20 indicated items such as ECC and higher 64-bit throughput, but that was ostensibly a process adjustment and rebuild rather than a respin.
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Vega 20 would be an entirely different ASIC though wouldn't it. Seeing as it has (allegedly!) 4k wide memory interface/HBM dies on two sides, and vega 10 only has memory interfaces on one side of its die.
 
Grall said:
Vega 20 would be an entirely different ASIC though wouldn't it. Seeing as it has (allegedly!) 4k wide memory interface/HBM dies on two sides, and vega 10 only has memory interfaces on one side of its die.
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My logic was that the process change alone would make it a different ASIC, but I had forgotten about the doubled bus width. Some of the features mentioned for that new ASIC were at various points alleged to be part of the Vega generation's initial implementation, so it's possible there are elements internal to Vega 10 that could be precursors or debugging versions of Vega 20's units.
 
Ryan Smith said:
At this point can anyone name what it is they'd like to see? It seems like this whole thing has transcended into a meme.
Click to expand...

I find your comment a bit funny.
Did you measure that perf/Watts increase of VEGA over Polaris?
Don't you wonder why AMDs biggest GPU arch change for some time leaves VEGA look like Fiji in many tests? Show me that magic of the binning rasterizer, primitive shader or whatever is your favourite hype train.
 
Tofu said:
I find your comment a bit funny.
Did you measure that perf/Watts increase of VEGA over Polaris?
Don't you wonder why AMDs biggest GPU arch change for some time leaves VEGA look like Fiji in many tests? Show me that magic of the binning rasterizer, primitive shader or whatever is your favourite hype train.
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My reading of the context from the cited forum is that these are features AMD will tout as being "new", which sounds like these are features they haven't talked about. Perf/W isn't a feature as much as an emergent property, and the primitive shaders and DSBR have already been disclosed. Perhaps if this refresh were marketed to have primitive++ shaders and Super-binning, those would be "new".

Granted, AMD has literally recycled slides from across product launches and said they were "new", so who knows.
 
Despoiler said:
The tell is that a shot of adrenaline makes you stronger. Why call it that if perf isn't going up?
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Software is always hard. Good thing is, you can fix it later. Why would anyone think, performance would not be going up? Just look at tried practices to make new driver releases appear as the next best thing to sliced bread. You just have to pick your cherries accordingly.
 
3dilettante said:
Some of the features mentioned for that new ASIC were at various points alleged to be part of the Vega generation's initial implementation, so it's possible there are elements internal to Vega 10 that could be precursors or debugging versions of Vega 20's units.
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Well, hopefully the advertised MIA features of vega 10 is not debugging precursors of anything, but actually real genuine working hardware which will start pulling its weight at some time soon in the future - just wait for that one magic driver that'll get the whole ball rolling! :p

(You can't blame me for hoping! I'm on the verge of splurging for two ASUS vegas...)
 
3dilettante said:
Some of the features mentioned for that new ASIC were at various points alleged to be part of the Vega generation's initial implementation, so it's possible there are elements internal to Vega 10 that could be precursors or debugging versions of Vega 20's units.
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But Vega20 is HPC silicon. It would bear somewhat distant relation to consumer stuff.
Besides, they talked said features in context of Vega10 anyway.
 
Bondrewd said:
But Vega20 is HPC silicon. It would bear somewhat distant relation to consumer stuff.
Besides, they talked said features in context of Vega10 anyway.
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A number of the features for Vega 20 were first mentioned in the context of leaks concerning Greenland, which was described as the lead GPU of the current generation, and what Vega 10 has been labelled at times. Perhaps that was in error, but it also does not contradict the idea that those features have been floating around outside of Vega 20.

Also somewhat notable is Vega 10 is showing up outside of client products, such as its Pro and Instinct lines. In the latter case, AMD's MI 25 specs needed to make note that they lacked on-die ECC, something that a supposed top-to-bottom GP104-GP100 competitor with a server oriented fabric (per Raja Koduri) would have had as an assumed checkbox in comparison to Tesla products, or AMD's own Hawaii.
 
CarstenS said:
Software is always hard. Good thing is, you can fix it later. Why would anyone think, performance would not be going up? Just look at tried practices to make new driver releases appear as the next best thing to sliced bread. You just have to pick your cherries accordingly.
Click to expand...
The question is 3-5% or 30-50%. Performance is likely to increase, but is it enough to justify running all the benchmarks again?

3dilettante said:
Also somewhat notable is Vega 10 is showing up outside of client products, such as its Pro and Instinct lines. In the latter case, AMD's MI 25 specs needed to make note that they lacked on-die ECC, something that a supposed top-to-bottom GP104-GP100 competitor with a server oriented fabric (per Raja Koduri) would have had as an assumed checkbox in comparison to Tesla products, or AMD's own Hawaii.
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In the case of ECC and some other pro features, it seems likely they are in all the Vegas. Just disabled and limited to pro products. Raja's statements in regards to Infinity featuring server features and consuming space would make little sense otherwise. Stripping ECC and leaving an over the top IF implementation. Still no idea what's different about it.
 
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