AMD and IBM planned to reveal the latest fruits of their collaborative effort at the International Electron Devices Meeting this week in Washington, D.C., said Gary Bronner, a distinguished engineer with IBM. The companies developed 65-nanometer manufacturing technology at IBM's wafer fabrication plant in East Fishkill, New York.
Future processors from both companies will use transistors that have been stretched in some ways, or compressed in others, to increase the speed at which electrons travel, said Nick Kepler, vice president of logic technology development at AMD. The new methods build upon strained silicon techniques the companies
introduced last year at the IEDM and implemented in chips earlier this year, he said.
