AMD Bulldozer Core Patent Diagrams

V3 said:
Also is Fusion = Bulldozer + GPU or is it a different core ? I am a little lost on AMD future lineup.
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"Fusion" is just the marketing name for APUs as far as I can tell. Hence all cpus with integrated graphics sail under that name.
For APU with Bulldozer cores you're looking at Trinity which is still more than a year away.
 
First Bulldozer board (AM3+ socket)?

sptzcn.jpg
 
entity279 said:
No 8 module BD is planned for desktop AFAIK. However, in terms of throughput at least, a 4 module BD with its 8 int cores @ 3-4 Ghz will be more than enough.

BD+ IGP is also will also not be released in the near future (Q2/3 2011).
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so presumably a 8-module processor would be a dual die opteron - taking place in existing motherboards.
 
http://www.techpowerup.com/138328/Bulldozer-50-Faster-than-Core-i7-and-Phenom-II.html
Here, take some salt. AMD reportedly gave out performance figures in a presentation to its partners, performance figures seen by DonanimHaber. It is reported that an 8-core processor based on the "Bulldozer" high-performance CPU architecture is pitched by its makers to have 50% higher performance than existing processors such as the Core i7 950 (4 cores, 8 threads), and Phenom II X6 1100T (6 cores). Very little is known about the processor, including at what clock speed the processor was running at, much less what other components were driving the test machine.

Taking this information into account, the said Bulldozer based processor should synthetically even outperform Core i7 980X six-core, Intel's fastest desktop processor in the market. Built from ground-up, the Bulldozer architecture focuses on greater inter-core communication and reconfigured ALU/FPU to achieve higher instructions per clock cycle (IPC) compared to the previous generation K10.5, on which its current Phenom II series processors are based. The processor is backed by new 9-series core logic, and a new AM3+ socket. AMD is expected to unveil this platform a little later this year.
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My mind always wanders back to this http://www.youtube.com/watch?v=G_n3wvsfq4Y
 
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well if they had of released Deneb instead of agena then they would have been in a much better place :LOL: . 65nm wasn't very kind to AMD.

That said AMD hasn't said anything about performance, the only real hint of anything i have seen from AMD is that even on there 16core bulldozer a 800mhz turbo to all cores while all core are running high load on the right kinds of workloads is possible ( which people then speculated to be INT based workloads). If this is true the biggest weapon AMD could have in the 4-8 core consumer market is massive turbo's.

i would actually find that an interesting question, if the only limitation for turbo is TDP ( no max turbo clock) what will be better for games, a 4 core bulldozer or an 8. you could then go further like does having each thread run on a different module on an 8 core( assume 2> <=4 threads) give better performance for a given TDP (120-130 WATTS) then a 4 core.

i know people here with far more knowledge then me have been very (whoa) about L1 size vs L2 latencies for misses etc but given the improved memory throughput the new prefectures and the new ALU's with such a large amount of front end resources im confident that there will be a good IPC increase over STARS. The question to be answered, is there anything to reduce the penalty of a L1 cache miss or just how accurate is the prefetching.

the other thing is AMD has released a hell of a lot more information about bulldozer then there was for Agena so there is far more confidence about any said performance numbers. AMD couldn't afford another Agena it would be about 8 death nails at once.
 
fellix said:
Bulldozer 'Orochi' wafer pictured

Not far from what we saw in the last year's GF presentation.
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Yes, but for one it's more symmetrical than PS job they showed before!
If someone is a close friend with Charlie, maybe he will be persuaded to leak the other, better pictures he has :devilish:.

L3 is definitely split in 4 slices, this will give AMD an easy job of creating different SKU's from faulty chips and reworking it for lower end markets as a 2 module (4 cores) + 4MB L3. Actually this is what we might get for Laptops sooner or later. Also it points out to ring-bus connected L3, similarly to SB and Beckton solutions.
 
I'd really like to see a closeup of one of its modules, espeicially how the FPU is laid out. Fusion w/ Bulldozer ought to be interesting; I'm wondering if they'll share resources between FPU and GPU eventually since they made claims for unifying address spaces and minting new instructions as well.
 
The dies in that picture look big, but we don't see the whole wafer and it is at an angle.
The margins of error for guesstimating the die size so far appear to be far too wide to really be sure.
I think it is probably over 300mm2, but that's a weak guess.
If someone has a good idea of how long the DDR interface should be, that would be a good starting point, since a whole side of the die (the short side?) is taken up by it.


On a side note:
It seems IBM and GF have done an about-face and will be going gate-last for the next node.

http://www.realworldtech.com/forums/index.cfm?action=detail&id=115949&threadid=115949&roomid=2
 
I imagine it must have been too late by now to change track for 22nm.

So, another 4 years before we see a process which has the checkbox features on desktop, sigh...
 
Zambezi stock clock-rate:

whatisit2.jpg


No info on whether this value is under load (turbo) or idle. Still impressive for a stock, though.
 
The clock appears too high to be for idle, if CnQ is on.
I would hope that is not max turbo, given that the design has done so much to slim things down to allow for clock scaling.
 
3dilettante said:
The clock appears too high to be for idle, if CnQ is on.
I would hope that is not max turbo, given that the design has done so much to slim things down to allow for clock scaling.
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Well, on one hand I would like to agree with you and hope this is full load on on all cores clock, but one another hand I realize this is 8 core CPU. Also by AMD's tradition early CPU samples are clocked conservatively by default.
 
I've checked for IOMMU on the chipsets, and found out it's available on all variants :LOL:, according to unambiguously wording of some pieces of news.

this with the backwards compatibilty means I can upgrade from AM2 and 2GB ddr2 to AM3+ and 4GB ddr3 while keeping the same CPU, and game under virtualized windows 7, eliminating the need for dual boot.
good news, a 890FX or 990FX board would cost me as much as CPU, graphics card and memory combined.
 
What this means....new news is good news! Waiting to upgrade to 6 cores Gulftown..or Bulldozer....quads are old skool.

http://www.eetimes.com/electronics-...na-eyes-petaflops-IBM-hits-5-GHz?pageNumber=2

Rick Merritt
2/21/2011 7:30 PM EST
AMD Bulldozer, Intel server CPUs

Advanced Micro Devices provided more details on its new Bulldozer core first described at Hot Chips in August. AMD senior engineer Hugh MacIntyre said the core enables 3.5 GHz performance is same power and thermal envelope as AMD's prior core design.

The core delivers linear performance across a range of frequencies and 0.8-1.3V voltages it will need to operate. It uses 213 million transistors in a 30.9mm2 block with 11 metal gates in a 32nm SOI process, he said.

A separate paper described Bulldozer's 40-entry instruction out-of-order scheduler and execution unit that can issue up to four instructions per cycle. The unit helps the core meet its target of delivering 90 percent of performance of past AMD cores with a significant reduction in area and power, said Michael Golden, another AMD engineer.
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A separate paper described Bulldozer's 40-entry instruction out-of-order scheduler and execution unit that can issue up to four instructions per cycle. The unit helps the core meet its target of delivering 90 percent of performance of past AMD cores with a significant reduction in area and power, said Michael Golden, another AMD engineer.
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This sounds like a miswording or a misquote.
The targets for Bulldozer's core were not set at 90% of earlier cores, it was supposed to be higher-performance.
 
3dilettante said:
This sounds like a miswording or a misquote.
The targets for Bulldozer's core were not set at 90% of earlier cores, it was supposed to be higher-performance.
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Ugh.

So the AMD quote of 50% faster than a 950 at lower clock...hmmm...
950: 4 cores x 1 = 4

BD: 8 cores x .9 x .8 (~20% slower per clock on Phenom II) = 5.76

Please say no!
 
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