A question about PPE/Xenon Core.

[Urian]

I am only talking about the logical core, Cache isn´t included.

Is true that the PPE isn´t a normal PowerPC processor and is derivated/succesor of the PowerPC Star series thas was created in the middle of nineties in Austin (TX)?

I say it because the RS64-IV has an architecture with a lot of similarities (the only difference is the VMX) with the PPE in Broadband Engine and one of the cores of Xenon. The PowerPC Star series were designed for multiple cores and the RS64-IV supported multithreading.

http://www.research.ibm.com/journal/rd/446/borkenhagen.html

 

[archie4oz]

Is true that the PPE isn´t a normal PowerPC processor and is derivated/succesor of the PowerPC Star series thas was created in the middle of nineties in Austin (TX)?

What praytell is a *normal* PowerPC?

 

[3dilettante]

I am only talking about the logical core, Cache isn´t included.

Is true that the PPE isn´t a normal PowerPC processor and is derivated/succesor of the PowerPC Star series thas was created in the middle of nineties in Austin (TX)?

It is true the PPE/Xenon core is not a standard PowerPC, and there are similarities in the emphasis on threading and reduced design complexity.

I say it because the RS64-IV has an architecture with a lot of similarities (the only difference is the VMX) with the PPE in Broadband Engine and one of the cores of Xenon. The PowerPC Star series were designed for multiple cores and the RS64-IV supported multithreading.

It borrows a number of ideas, though it has a number of differences, perhaps in part because it was designed for the manufacturing process available at the time.

The SStar series relied on significantly larger caches and coarse multithreading.
The PPE does not rely on large L1 cache sizes, though it has an integrated L2 to help make up for that. The PPE also has integrated branch prediction logic, no doubt because its pipeline is way longer than the SStar's ( 5 vs 23 stages).
SStar's use of a taken branch buffer is not found in the PPE, perhaps in part because the length of the pipeline is such that the buffer would be too large to be useful.

The SMT threading of the PPE means that instructions go through the core simultaneously, unlike the SStar chip. It looks like the PPE actually dispatches 2 instructions from each thread every other cycle.
The Star chip only starts to issue from the other thread on an event like a mispredict or a cache miss.

The PPE is also narrower than SStar, being dual issue vs. 4-way superscalar. SStar also looks to be Out of Order.

 

[Urian]

You have said all the reasons why I think that the POWER Processor Element is more in part of the family of the Star Series than the PowerPC used in the Macintosh, they seem to operate similar in a lot of ways.

 

[3dilettante]

It's more that they share a few common goals.

The fact that the PPE uses SMT, is in-order, has a long pipeline, has half the issue width, and has branch prediction weighs against it being more than a cousin once or twice removed.

to summarize:
The SStar has about as many differences from the PPE as it does a processor like the G4.

 

[ADEX]

Is true that the PPE isn´t a normal PowerPC processor and is derivated/succesor of the PowerPC Star series thas was created in the middle of nineties in Austin (TX)?

No, it appears to be a derivative of an experimental 1GHz processor developed in the late 90s called GuTS, the first 1GHz CMOS processor, 3 years before anyone else got to that speed.

The first version only implemented a partial version of the PowerPC ISA but a later version in 2000 was fully compatible.