A few questions on NV30, NV35

And, to compound the problem, as you try to overclock a given chip you get more attenuation of the signal on your interconnect lines. That is why overclockers have to increase the power supply voltage on the CPU (which seems counter-intuitive since it increases the heat produced).

 

Overclockers then add really exotic cooling solutions.

 

I agree with your statements, and to clarify further, it is my understanding (and I could be wrong) that the chip's clock distribution network (called a 'clock tree') dissipates a significant portion of the die's total power budget, 30-40% being typical.

The clock-distribution network contains a lot of buffer (amplifer) circuits whose sole purpose is to drive the clock-input of every flipflop. The buffers are regular CMOS transistors (like everything else on the die), but they don't directly contribute to the chip's computational function. For the non-EEs out there, you can think of these extra transistors as 'support circuitry'.

I guess my key point is that the clock-tree contains a very small percentage of the die's total transistors. Yet those few transistors (and their interconnect traces) burn a DISPROPORTIONATE amount of power relative to the rest of the chip. "Clock gating" lets the designer turn off selected parts of the clock-tree (by freezing the state of the input to to the clock-branch's root, effectively idling the power-hungry amplifiers in that branch.)

 

May I continue this mutual admiration society by agreeing wholeheartedly with that?

An example is that I suspect that most of the improvements that went into the Athlon 4 for power reduction - which was quite successful, at least 30% down - were improving the whole clock domain and gating side. It can make a massive difference.

ATI and nvidia are both pretty good at this, they both look-ahead with their designs to the mobile chip.

 

Chuckle, that doesn't look very good, does it?

Anyways, what I meant is I'm not championing that the NV30 IS going to be significantly faster in clock speed. I'm just debunking the (paraphrased) 'it probably won't be' statement.

But, to answer your question, you can peruse opencores.org and they've got a few things there, but not much mention of gate count for different blocks.

You could also try www.design-reuse.com as a place to peruse licensable IP (you have to register to access the databases). Usually there's a gatecount, etc for all the different pieces listed there, plus contact information for the different companies.

www.xilinx.com and www.altera.com usually have some IP to search through for all sorts of different functionality (though no RAMDAC stuff, thats mixed signal and not FPGA stuff), though they'll probably list all of their stuff in functional units (or slices, or macro cells, etc) which don't map to gates or transistors very well.

 

Just to follow up:

http://www.nurlogic.com/datasheets/pdfs/ds_tsmc_15_lv_360mhz_vdac_a1.pdf

www.ledasys.com has a 10bit 360mhz ramdac for .15u that is approximately 1 mm2 (or approximately 75-100k gates, or somewhere less than 1M transistors)

http://www.enablingtechnology.com/clients.html (seems to be the provider for ArtX's RAMDACs, but nothing on their website talks about size)

 

That's 10 bit per channel.

By the way, if you register at design-reuse.com, don't put a real phone number unless you want sales calls. They automatically feed your contact info when you request datasheets, etc. to the company in question.

I browsed that ledasys part just 5 minutes ago and just got a call.

 

Um, just to be clear:

Nobody said "it probably won't be faster." So you are dubunking something that nobody said.

We said (paraphrase) "everyone seems to assume NV30 will have a higher clock without question...however, there is reason to believe it may not be faster..."

We are dubunking the (paraphrased) "I see no reason to suggest NV30 will be slower" statements.

 

Anyone remembers my thread?

All the information there is correct, so I don't understand why discussions such as "will the nv30 be faster in clock speeds than the r300" are still going on...

 

Luckily...no.

 

40 bit DAC per channel?

I doubt it, for any part now, or likely in the future.

 

Some designs like the P3-S and P3-M designs (512kb l2 cache) are much less dependent on frequency because a lot of power is consumed by the large cache and its static current. ~30% increase in frequency means only ~10% increase in power dissipation.

 

I'm not sure I totally agree that my statement was so totally idiotic, but I removed it, since that particular contention obviously isn't going anywhere anyway.

 

It does seem like we're kind of going around in circles doesn't it?

 

Interesting. Although GPU's don't contain the cache sizes of GPU's, there is usually quite a bit of SRAM blocks.

Not sure how this would make a difference... or if we'd know if it was