A few questions on NV30, NV35

[kid_crisis]

And, to compound the problem, as you try to overclock a given chip you get more attenuation of the signal on your interconnect lines. That is why overclockers have to increase the power supply voltage on the CPU (which seems counter-intuitive since it increases the heat produced).

 

[Colourless]

Overclockers then add really exotic cooling solutions.

 

[asicnewbie]

pascal covers this and more, but I thought I'd add a touch more detail:

IIRC, heat is proportional to the square of the voltage and to the total number of transistor state changes per unit time (therefore, it is proportional to frequency).

This is why clock gating (not clocking any unused part of the chip) is a big thing in mobile parts.

I agree with your statements, and to clarify further, it is my understanding (and I could be wrong) that the chip's clock distribution network (called a 'clock tree') dissipates a significant portion of the die's total power budget, 30-40% being typical.

The clock-distribution network contains a lot of buffer (amplifer) circuits whose sole purpose is to drive the clock-input of every flipflop. The buffers are regular CMOS transistors (like everything else on the die), but they don't directly contribute to the chip's computational function. For the non-EEs out there, you can think of these extra transistors as 'support circuitry'.

I guess my key point is that the clock-tree contains a very small percentage of the die's total transistors. Yet those few transistors (and their interconnect traces) burn a DISPROPORTIONATE amount of power relative to the rest of the chip. "Clock gating" lets the designer turn off selected parts of the clock-tree (by freezing the state of the input to to the clock-branch's root, effectively idling the power-hungry amplifiers in that branch.)

 

[Dio]

May I continue this mutual admiration society by agreeing wholeheartedly with that?

An example is that I suspect that most of the improvements that went into the Athlon 4 for power reduction - which was quite successful, at least 30% down - were improving the whole clock domain and gating side. It can make a massive difference.

ATI and nvidia are both pretty good at this, they both look-ahead with their designs to the mobile chip.

 

[Bigus Dickus]

All I can say is you guys are totally full of shit....saying that there's nothing to suggest it won't be (significantly) faster is just ridiculous.

Yeah, thats exactly what I said. I am so full of shit, aren't I?

Did you even read the whole thread? I hate to be combative here, but constantly CONSTANTLY people don't read half of what's written, and then invent the other half. I said nothing of the sort.

Let me state very clearly: I'm not saying that NV30 will be faster, I'm stating that there's nothing out there to suggest that it won't be...

Now, putting all this squabbling aside, is someone willing to even venture a guess on one of my original questions: how many transistors would an integrated RAMDAC take, or 8 TMU's take?

This is more just for my own personal curiosity. I'm not looking for a definitive answer, just a ballpark. You know, like "a few thousand per TMU" or "a few million per TMU." That would be good enough to satisfy my curiosity. I realize that specific designs will result in differences in final transistor count, but my guess is that TMU or a RAMDAC will take roughly the same space no matter who designed it.

OpenGL Guy, Mintmaster... anyone?

 

[RussSchultz]

Chuckle, that doesn't look very good, does it?

Anyways, what I meant is I'm not championing that the NV30 IS going to be significantly faster in clock speed. I'm just debunking the (paraphrased) 'it probably won't be' statement.

But, to answer your question, you can peruse opencores.org and they've got a few things there, but not much mention of gate count for different blocks.

You could also try www.design-reuse.com as a place to peruse licensable IP (you have to register to access the databases). Usually there's a gatecount, etc for all the different pieces listed there, plus contact information for the different companies.

www.xilinx.com and www.altera.com usually have some IP to search through for all sorts of different functionality (though no RAMDAC stuff, thats mixed signal and not FPGA stuff), though they'll probably list all of their stuff in functional units (or slices, or macro cells, etc) which don't map to gates or transistors very well.

 

[Bigus Dickus]

Thanks for the links. Looks like some interesting stuff.

 

[RussSchultz]

Just to follow up:

http://www.nurlogic.com/datasheets/pdfs/ds_tsmc_15_lv_360mhz_vdac_a1.pdf

www.ledasys.com has a 10bit 360mhz ramdac for .15u that is approximately 1 mm2 (or approximately 75-100k gates, or somewhere less than 1M transistors)

http://www.enablingtechnology.com/clients.html (seems to be the provider for ArtX's RAMDACs, but nothing on their website talks about size)

 

[Bigus Dickus]

Just to follow up:
www.ledasys.com has a 10bit 360mhz ramdac for .15u that is approximately 1 mm2 (or approximately 75-100k gates, or somewhere less than 1M transistors)

You think that would be 10-bit/channel or 10-bit total?

On a related note, since a discussion at another forum is on this line, is the R300 and/or NV30 rumored/said to be capable of 40-bit DAC and output?

 

[RussSchultz]

That's 10 bit per channel.

By the way, if you register at design-reuse.com, don't put a real phone number unless you want sales calls. They automatically feed your contact info when you request datasheets, etc. to the company in question.

I browsed that ledasys part just 5 minutes ago and just got a call.

 

[Joe DeFuria]

Um, just to be clear:

I'm just debunking the (paraphrased) 'it probably won't be' statement.

Nobody said "it probably won't be faster." So you are dubunking something that nobody said.

We said (paraphrase) "everyone seems to assume NV30 will have a higher clock without question...however, there is reason to believe it may not be faster..."

We are dubunking the (paraphrased) "I see no reason to suggest NV30 will be slower" statements.

 

[alexsok]

Anyone remembers my thread?

All the information there is correct, so I don't understand why discussions such as "will the nv30 be faster in clock speeds than the r300" are still going on...

 

[Joe DeFuria]

Anyone remembers my thread?

Luckily...no.

 

[RussSchultz]

40 bit DAC per channel?

I doubt it, for any part now, or likely in the future.

 

[pascal]

May I continue this mutual admiration society by agreeing wholeheartedly with that?

An example is that I suspect that most of the improvements that went into the Athlon 4 for power reduction - which was quite successful, at least 30% down - were improving the whole clock domain and gating side. It can make a massive difference.

ATI and nvidia are both pretty good at this, they both look-ahead with their designs to the mobile chip.

Some designs like the P3-S and P3-M designs (512kb l2 cache) are much less dependent on frequency because a lot of power is consumed by the large cache and its static current. ~30% increase in frequency means only ~10% increase in power dissipation.

 

[Bigus Dickus]

40 bit DAC per channel?

I doubt it, for any part now, or likely in the future.

Actually, I meant 40-bit total, as opposed to the 32-bit we currently have.

As in, will either the NV30 or R300 (or Parhelia) support higher color depths on actual displays?

 

[Nagorak]

All I can say... ...is just ridiculous.

Can You please edit out this sentence? Why do You disqualify Your arguments with such an idiotic statement.

thanks

I'm not sure I totally agree that my statement was so totally idiotic, but I removed it, since that particular contention obviously isn't going anywhere anyway.

 

[Nagorak]

Um, just to be clear:

I'm just debunking the (paraphrased) 'it probably won't be' statement.

Nobody said "it probably won't be faster." So you are dubunking something that nobody said.

We said (paraphrase) "everyone seems to assume NV30 will have a higher clock without question...however, there is reason to believe it may not be faster..."

We are dubunking the (paraphrased) "I see no reason to suggest NV30 will be slower" statements.

It does seem like we're kind of going around in circles doesn't it?

 

[Dio]

Some designs like the P3-S and P3-M designs (512kb l2 cache) are much less dependent on frequency because a lot of power is consumed by the large cache and its static current. ~30% increase in frequency means only ~10% increase in power dissipation.

Interesting. Although GPU's don't contain the cache sizes of GPU's, there is usually quite a bit of SRAM blocks.

Not sure how this would make a difference... or if we'd know if it was