A few questions on NV30, NV35

[Lessard]

I can't help but notice that NVIDIA's historical timing between NVx0 and NVx5 generations is anything but 6 months.

NV10 was the GeForce256. Next was the DDR version, and then we got the NV15 (GF2) a year or so later. The "refresh" was not the NV15 core, but simply the same NV10 core with DDR memory.

You're wrong ! DDR version came only 2/3 months later and it was not a refresh ... Geforce2 came 6 months later than the Geforce1 SDR

 

[multigl2]

you cant make a direct comparison based onm transistor count. things get better when you find out how much is logic and how much cache. The radeon9700 with slightly over 110Mt's most likely has very aggresive caching schemes (read: a good chunk of cache) and where the the NV30 has ~120 w/ 2 TMU's per-pipe, its possible that if the designs are really similar, that NVIDIA decided to not have 4 full Vec4 units like the R300 and Parhelia.... this could account for the presumed earlier polygon rates.

 

[asicnewbie]

But is all else equal? Jen Hsun did say they were using the 0.13um WITH copper interconnects for NV30. Does TSMC's standard 0.15um process use copper? (as opposed to aluminum)

You can visit TSMC's website and get an overview of their CMOS logic processes (0.13, 0.15, 0.18.)

According to http://www.tsmc.com/download/enliterature/015_bro_2002.pdf ,
copper interconnect is available as two options : either the 'top 2 interconnect' layers or 'all-layers' (up to all 7.) I assume either copper option costs more than the standard aluminum interconnect.

In the past, using copper interconnect had a negative impact on yield. I don't know whether that is true of TSMC's process line.

 

[Fuz]

I got a question. Why is it that CPUs are going in the GHZ range, while gpus are still in the low megahertz? Is it a heating problem?

Here you go! http://www.beyond3d.com/forum/viewtopic.php?p=19348&highlight=#19348

Hope that answers your question.

Fuz

 

[Dio]

(Multiply by 6 to get transistors)
USB1.0 cores are approximately 20k gates

Not necessarily the case. As clock speed increases some designs require extra transistors/gate and even extra gates/block. When I was in chip design we gave up counting gates and moved to counting silicon area per unit because it was less confusing (we had some units we were thinking of running at 2x clock and the transistor/gate counts were all over the shop).

 

[Dio]

NVIDIA are trying to something special here... ATI have already done it so NVIDIA will not rest unless they have the FASTEST performing chip on the market, period. I say that because ever since the TNT2 nothing has beaten NVIDIA's performance

Ahh, but in that case, do nvidia know how to play catch-up any more or have they become complacent?

 

[RussSchultz]

(Multiply by 6 to get transistors)
USB1.0 cores are approximately 20k gates

Not necessarily the case. As clock speed increases some designs require extra transistors/gate and even extra gates/block. When I was in chip design we gave up counting gates and moved to counting silicon area per unit because it was less confusing (we had some units we were thinking of running at 2x clock and the transistor/gate counts were all over the shop).

I'm just quoting numbers given on vendor websites, and by vendors themselves.

Edit: Aaah, you mean 6 per gate? That was just a SWAG on my part.

 

[pascal]

1-The difference between TSMC .15 micron and .13 micron process are small: http://www.tsmc.com/english/technology/t0101.htm

TSMC is working diligently on the 0.13-Micron process, with easy integration a top priority during its development. The new technology will reduce die size by more than 20 percent and provide performance improvements for 30 percent when it is compared to the same device on TSMC 0.15-Micron process technology. When compared to the 0.18-Micron process, the new 0.13-Micron process results in less than 60 percent the die size and nearly 70 percent improvement in performance

2-The R300 is using extra power beyond AGP specs. It is like a runner having an extra source of oxygen.

3-The R300 has a good hand tweaked design.

4- The transistors count difference is around 10% and means nothing.

From the info we have we can not conclude anyone faster.
We need more info.

 

[Dio]

Aaah, you mean 6 per gate? That was just a SWAG on my part.

That's what I was aiming for. AFAIK 6 is certainly a reasonable guestimate... but there's no guaranteed relation.

 

[Bjorn]

1-The difference between TSMC .15 micron and .13 micron process are small

30% is a lot imo.

2-The R300 is using extra power beyond AGP specs. It is like a runner having an extra source of oxygen.

I'm having a hard time to see why this should be a benefit for ATi.
It's something that they had to do because of the 0.15 micron process,amount of transistors and clockspeed.

3-The R300 has a good hand tweaked design.

And the NV30 has not ?

4- The transistors count difference is around 10% and means nothing.

Nothing ????

But i agree, we definitely need more info before we conclude anything.

 

[Joe DeFuria]

I'm having a hard time to see why this should be a benefit for ATi.
It's something that they had to do because of the 0.15 micron process,amount of transistors and clockspeed.

Well, exactly...the benefit to ATI is the last thing you said: clockspeed.

Look at it this way. (I'm going to over simplify things for the sake of clarity.)

For a given number of transistors, you are limited to a certain clock rate in order to stay within certain power consumption limits. We also know that the smaller the process size, the less power consumed.

So let's say you design a 110 million, 0.15 micron part to consume a maximum 40 watts of power, to stay within AGP spec. Say that this would mean a design with a target maxiumum of 250Mhz operation. Any faster and you'd consume too much power.

Now, let's say that on 0.13 micron, you can clock at 360 Mhz (30% faster than 0.15) for the same number of transistors and still be at 40 watts.

But let's take the 0.15 micron case, and say you don't care about the AGP spec and will provide power from the power supply....say 60 watts of power total. Now, you can clock higher than 275Mhz...maybe up to 375 Mhz. (Don't know if the power / clock rate relationship is linear....forgot all elemetary physics....)

So, if nVidia's NV30 stays within AGP spec and doesn't require a connector, then this means that R-300 consumes more power. That means that any inherent clock speed advantage that NV-30 would have over R-300 based solely on process size would be diminshed (or eliminated), depending on actual power consumption differences.

 

[RussSchultz]

The power benefits of moving to a smaller technology outweigh the clock benefits (one is a squared relationship, the other is not).

You can increase clock speed by up to 20%, but power will go down by 40% (assuming all digital), for example, given the same design when going from .15u to .13u.

So, assuming the same design that runs OK on only 100% AGP power in .15u at 300 MHz

You should be able to run that same design on 80% AGP power in .13u at 360Mhz (or 420MHz, if you were limited by power, and not timing).

Of course, this is a rule of thumb, and not set in stone. Analog doesn't scale well (and all these parts have built in RAMDACs), and your upper speed can be limited by routing and not gate delay, and not be affected as much by process shrink.

 

[pascal]

Russ

The power will depend on the vcore and the TSMC .13 micron process has 3 different possible vcores (1.0v, 1.2v, 1.5v) and the .15 micron has 2 differents vcores possible (1.2v , 1.5v). The die size (with the same design) will reduce up to 20%.

What are the vcore used by R300 and NV30?

We cannot conclude 40% of power savings, can we?


All what I say is that we cant conclude anything based on the info we have. We need more info.

 

[Bjorn]

Look at it this way. (I'm going to over simplify things for the sake of clarity.)
.....

Ok, i'm going to over simplify this

We'll assume that:

1: Nvidia can clock the NV30 at 300 MHz without extra power
2: Nvidia can clock the NV30 at 400 MHz with extra power

What would you think they would do ?

I would think that they would do that and then the "benefit" of the R300 won't be a benefit anymore.

 

[pascal]

Look at it this way. (I'm going to over simplify things for the sake of clarity.)
.....

Ok, i'm going to over simplify this

We'll assume that:

1: Nvidia can clock the NV30 at 300 MHz without extra power
2: Nvidia can clock the NV30 at 400 MHz with extra power

What would you think they would do ?

I would think that they would do that and then the "benefit" of the R300 won't be a benefit anymore.

Bjorn

What can be a performance benefit may not be a marketing benefit specially with OEMs.

 

[Bjorn]

Bjorn

What can be a performance benefit may not be a marketing benefit specially with OEMs.

So Nvidia would accept 300 MHz instead of 400 just to get rid of the extra power connector for their high end card that's supposed to battle with the R9700 that has the extra power connector ?

And i doubt that the extra power connector would be a problem for marketing the NV30. I would think that a 100 MHz more then ATi's top card would sell a lot more cards then "look , we don't have to use a extra power connector".

 

[kid_crisis]

According to http://www.tsmc.com/download/enliterature/015_bro_2002.pdf ,
copper interconnect is available as two options : either the 'top 2 interconnect' layers or 'all-layers' (up to all 7.) I assume either copper option costs more than the standard aluminum interconnect.

In the past, using copper interconnect had a negative impact on yield. I don't know whether that is true of TSMC's process line.

Thanks for the link Asicnewbie. Yes, from what I've heard copper is a much harder process to get high reliability on. I think most of the other big fabs are using copper now though, so I don't think the challenges are insurmountable.

 

[pascal]

1-The difference between TSMC .15 micron and .13 micron process are small

30% is a lot imo.

It is less than the difference between .18 micron and .13micron.

2-The R300 is using extra power beyond AGP specs. It is like a runner having an extra source of oxygen.

I'm having a hard time to see why this should be a benefit for ATi.
It's something that they had to do because of the 0.15 micron process,amount of transistors and clockspeed.

Ok lets speculate that the AGP spec limit the power to 20w and R300 used 24w (20% more) and that NV30 stay in the limit then the smaller process advantage will be partially negated by the extra power resource.

3-The R300 has a good hand tweaked design.

And the NV30 has not ?

What I mean is that there are no obvious design problems.

4- The transistors count difference is around 10% and means nothing.

Nothing ????

But i agree, we definitely need more info before we conclude anything.

Yeah, nothing the P4 has more transistors than the Athlon, what can you conclude from that?

 

[Joe DeFuria]

1: Nvidia can clock the NV30 at 300 MHz without extra power
2: Nvidia can clock the NV30 at 400 MHz with extra power

What would you think they would do ?

It's not that simple, Bjorn.

You have to TARGET your part at a Mhz / power band during design. You don't just say "OK, we built this thing to consume 40 watts @ 300 Mhz.....but hey, we can just slap on a power connector and take it up to 400!"

ATI (apparently) designed R-300 to be right at the AGP power consumption limits. Not surprising given the number of transistors on 0.15. I'm not sure they always intended to use the power connector, but at the very least it was a contingency in case it was required for stability.

The question is, what is the TARGET power consumption limit of the NV30 design? I'll say this, if the NV30 is pushing AGP power consumption limits with 0.13, with a similar number of transistors compared to R-300, it's not a very power efficient design.

 

[Bjorn]

You have to TARGET your part at a Mhz / power band during design. You don't just say "OK, we built this thing to consume 40 watts @ 300 Mhz.....but hey, we can just slap on a power connector and take it up to 400!"

ATI (apparently) designed R-300 to be right at the AGP power consumption limits. Not surprising given the number of transistors on 0.15. I'm not sure they always intended to use the power connector, but at the very least it was a contingency in case it was required for stability.

The question is, what is the TARGET power consumption limit of the NV30 design? I'll say this, if the NV30 is pushing AGP power consumption limits with 0.13, with a similar number of transistors compared to R-300, it's not a very power efficient design.

I'm perfectly aware of that it's not that simple.
Otherwise we would have had a ti4600 plus super turbo with an extra power connector a long time ago.

I just want to get rid of the idea the the extra power connector is some kinda of extra benefit for the R9700 like Pascal made made it out to be.

It's something ATi had to do to get a stable card since they are on a 0.15 micron process and uses lot's of transistors.

As you said yourself:

I'm not sure they always intended to use the power connector, but at the very least it was a contingency in case it was required for stability.