It appears that 3dhq secret project, Revenge, has been canceled:
http://www.tdhq.com/
So what was Revenge, you might ask? 3dhq has provided the details in this Powerpoint presentation: http://kirby.colorado.edu/jrr/revenge.ppt
In addition, the speck sheet (which for some reason doesn't exactly match the PP presentation) has been made available in this thread by 3dhq personnel:
Apparently, a licensing agreement has been reached:
The overview of some ground-braking, patent-pending technologies developed for Revenge has also been provided. The summary of some of the patents follows:
Additional information:
http://www.tdhq.com/
So what was Revenge, you might ask? 3dhq has provided the details in this Powerpoint presentation: http://kirby.colorado.edu/jrr/revenge.ppt
In addition, the speck sheet (which for some reason doesn't exactly match the PP presentation) has been made available in this thread by 3dhq personnel:
Code:
96M+ Triangles/s
0.13 micron 8 w power consumption with approx 36 million transistors.
3200MP/s fill rate
32 fully featured pixels per clock.
128 bit internal Precision with 64 bit Zbuffer support.
Hardware Deferred Rendering Capability (Tiling).
1024 bits wide Memory Crossbar divided into 4 256 bit pathways.
96 Texel cache Stages upto 16 shared rendering pathways with 2tmus per pipe.
32 layer multitexture in a single pass.
Upto 1000 K + triangles per frame.
Capable of 1600 Mega pixels in a single pass with 16 textures, Trilinear Anisotropic Filtering and 24 bit textures with 4x Multisampling.
Free Anisotropic Filtering with AA enabled.
Upto 256 tap Anisotropy possible.
Hardware Displacement Mapping and full DX9.1+ Capability.
Upto 78GB/s fill rate.
Full color compression and Bandwidth saving capabilities.
Multi-sample anti aliasing (Gamma corrected and rotated grid jittered samples) upto 16 samples possible.
Super Sampling upto 8X jittered grid.
Full support for cinematic factions such as motion blurs soft reflectance and soft shadows.
Off Chip geometry co-processing Industry innovation in TNL solution
Twin Risc TNL engines for Advanced pixel/Vertex shading calculations
TNL units hyper threaded for optimal CPU like performance.
PS /VS Shaders 1.0 to 2.0 + specs
Full DXTC 1 to 5 Support with FXT1 support in Hardware.
Fully microcode updatable Architecture.
500 + MHZ internal and DDR clock.
Multichip Capable Architecture MCA.
Upto 4 chips in MCA. 9.6 GPixel/s possible.
AGP 8X AGP 3.0 Spec.
32MB to 256MB frame bufferApparently, a licensing agreement has been reached:
The overview of some ground-braking, patent-pending technologies developed for Revenge has also been provided. The summary of some of the patents follows:
Circuit for processing RISC instructions for 96 bit Pipeline texture stage. Vertex and Pixel Shader Implementation routines 2.0+
An apparatus and method for prioritizing interrupt requests in a RISC processor. By utilizing hardware to prioritize the requests, processor time is reduced. The acknowledge signal (Ack(0)-Ack) from a priority resolve circuit (50) selects the given service routine entry to branch instruction generating circuit (56, 5. A lower priority service routine can be interrupted by a higher priority reply. Circuit Accelerates Video Bit signals by dividing itself into multiple synchronized Shader arrays, the shader array is 196 bit precision with 32 alpha channels. Speed tessellation allows RISC processor to emulate all pixel shader versions from 1.0 to 2.0+ HLSL AND CG capable.
Additional information:
. The 1024-bit bus (1204 bit * 500 MHz DDR = 128 GB/s) makes little sense - with the stated fillrate, color compression, and tiling, I'd estimate the bus to reach ~20-40% utilization, making everybody pay through the nose for an ultra-expensive and uselessly wide bus. Also, for something that is supposed to crush NV/ATI into fine dust, a limitation of 1M triangles per frame is ... weak.
