* Up to 1.6GHz processing performance for each ARM v7 compliant core
* 16,600 DMIPS performance at less than 10 watts
* "Heterogeneous multiprocessing" (SMP/AMP/Mixed) with "hardware-based Cache Coherence"
* Up to 2MB system level two cache
* 64-bit DDR2/DDR3/DDR3L memory interface with ECC support at up to 800MHz clock rates
* 4 PCI-e Gen 2.0 units
* 4 enterprise class Gigabit networking ports
* Up to 16 high speed Marvell SERDES lanes with multi functionality (PCI-e, SATA, SGMII, QSGMII)
* Multiple USB ports
from http://arstechnica.com/business/new...ts-back-at-chipzilla-with-new-server-chip.ars
* 16,600 DMIPS performance at less than 10 watts
* "Heterogeneous multiprocessing" (SMP/AMP/Mixed) with "hardware-based Cache Coherence"
* Up to 2MB system level two cache
* 64-bit DDR2/DDR3/DDR3L memory interface with ECC support at up to 800MHz clock rates
* 4 PCI-e Gen 2.0 units
* 4 enterprise class Gigabit networking ports
* Up to 16 high speed Marvell SERDES lanes with multi functionality (PCI-e, SATA, SGMII, QSGMII)
* Multiple USB ports
from http://arstechnica.com/business/new...ts-back-at-chipzilla-with-new-server-chip.ars