Lecram25 said:the XG40 is 128bit too. But it seems that by bridging them together, they claim to get a 256bit memory bus, which is what they plan on doing with the XG45, dual chip solution...
That's the exact problem with AFR though and it's by far not a 256bit or even 256bit equivalent bus. What's the available bandwidth between the two chips? Somewhat above 2GB/s...
Albeit AFR and SLI (the latter being in fact a far better idea if further refined) are quite different methods the constant problems were that each chip always required it's own dedicated ram and triangle setup was never shared between chips.
In the case of the Volari it's oversimplyfied a Master and a Slave chip where one chip takes on the even frames and the other the odd frames (Master= Frame 1, Slave= Frame 2, Master= Frame 3....etc.); not exactly but I prefer that simple explanation. In my mind per frame and per chip there's only (with 350MHz DDR) a maximum theoretical bandwidth of 11.2GB/s available.
At 325MHz and 16 total TMUs the bandwidth requirement should be at 20.8GB/sec (gee I wonder why ATI/NV while increasing the amount of texture ops on future products have also raised the available memory bandwidth up the wazoo...).
Now a funky speculation on a dual XG45 config; for PS/VS2.0 and XG40 they had ~80M transistors per chip * 2 = 160M transistors and two molex connectors. A conservative estimate for PS/VS3.0 could point at ~120M transistors (or more) * 2 = 240M transistors...
That's the exact reason why I'm saying that they need to change their design philosophy from scratch and especially get rid of multi-chip approaches. Or at least get rid of that hideous AFR approach and assign viewports to chips, so that they finally can share triangle setup and truly double throughput....