TSMC Unveils Details of 5nm CMOS Production Technology

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TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019

https://semiwiki.com/semiconductor-manufacturers/tsmc/282339-tsmc-unveils-details-of-5nm-cmos-production-technology-platform-featuring-euv-and-high-mobility-channel-finfets-at-iedm2019

Back in April, 2019, TSMC announced that they were introducing their 5 nm technology in risk production and now at IEDM 2019 they brought forth a detailed description of the process which has passed 1000 hour HTOL and will be in high volume production in 1H 2020. This 5nm technology is a full node scaling from 7nm using smart scaling of major design rules (gate, fin and Mx/Vx pitches) for improved yield featuring an SRAM cell of 0.021um2 and a declining defect density D0 that is ahead of plan.
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I would have liked to see some kind of approximate number for the relative density of the HPC variation of the process. Not that we ever got one for 7nm.
Oh well, I guess we would have to look at the finished products anyway.
 
TSMC expected to begin volume production of 5nm in April
March 12, 2020
The semiconductor manufacturer TSMC is now looking to scale up its production of 5nm chips, with volume production set to start in April according to industry sources cited by the DigiTimes. TSMC’s “process capacity” is also said to be “fully booked by clients”, so clearly its 5nm chips are in high demand. Apple’s A-series chip production usually starts in April-May, so the process seems to be going according to plans.

All of this – of course – comes with a hefty price tag. According to Tom’s Hardware, TSMC’s 5nm process will deliver ‘a 1.84x improvement in density.’ The new technology is also expected to bring 15% higher performance using the same amount of electricity, or 30% lower power consumption with maintained performance.
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https://www.kitguru.net/channel/christopher-nohall/tsmc-expected-to-begin-volume-production-of-5nm-in-april/
 
Marvell talks about TSMC’s 5nm process
August 25, 2020
Today they are actually releasing a set of very interesting numbers for 5nm and better yet it appears to be about as close to the real world as you can ask for without specific product details. Since their ASIC products are designed for customers, Marvell can’t really talk directly about them. As you can see from the two charts below, they can talk about their IP blocks and that gets you most of the way there.
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The blocks on this slide are the same ones as the prior slide, once again normalized to the same design on 7nm. The middle green column is a simple port to the 5nm and shows a >20% average energy use advantage. If you reduce the voltage to ISO performance you get the dark blue column which almost doubles that average gain. Given that a lot of the ASICs Marvell builds are embedded devices with specific performance targets, this is a realistic scenario.
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So in the end what do we have? Marvell is talking about TSMC’s 5nm process and doing so with numbers. Better yet they aren’t talking about vague numbers that define the limits of the process technology, they are talking about real world performance and area values for their IP.
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Marvell_5_vs_7_power-768x405.jpg

https://semiaccurate.com/2020/08/25/marvell-talks-about-tsmcs-5nm-process/
 
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