TSMC Moving to 80nm

[Jawed]

http://www.theinquirer.net/?article=29033

I changed the title slightly.

The firm will kick off the move with its GT process, move to the high speed HS process in February, and low power processes in March. It will introduce a special process in Q3 of this year to provide both low active and standby power.

So, ahem, will NVidia ever release 90nm desktop parts, or will it start at 80nm?

Jawed

 

[Martin Eddy]

Would they risk it though?

 

[satein]

So, ahem, will NVidia ever release 90nm desktop parts, or will it start at 80nm?

Jawed

I don't think INQ ment GT by 7800GT, it would be a GT (short wording of something) process as it stated in the next phase that "move to the high speed HS process in February". Migth it be refered as a process name more than a product? As NV have no HS chip... I might be wrong... just guessing.

 

[Arty]

*cough*R590*cough*

 

[Cowboy X]

Didn't ATI already say that they had parts slated for 80 nm ? Or was that just rumoured ? According to the article it is a direct shrink of their 90 nm process ............. does this mean 80nm LowK ?? Or not ?

This would be interesting ............... 80 nm highK with good savings or 90 nm lowK with high speeds .

Just wondering .

 

[Razor1]

Yep it should come with Low-k, actually are there any process smaller then .11 without some kind of insulation? I'm not sure but I think there aren't.

 

[karlotta]

Yep it should come with Low-k, actually are there any process smaller then .11 without some kind of insulation? I'm not sure but I think there aren't.

I dont think so at TSMC. But some others have 90nm non Low~k. (UMC?)

 

[Razor1]

Don't think so, I think the problem when you start getting to this small of a size, they need some type of insulater to prevent excessive leakage.

 

[Razor1]

Don't think so, I think the problem when you start getting to this small of a size, they need some type of insulater to prevent excessive leakage. They might have .09 if I remember correctly.

No they don't

According to eeTimes , UMC executives fired back at a ChipWorks analysis of its 90-nm technology, saying the process can be offered in either a low-k and fluoro-silicate glass configuration. UMC also claims that its 90-nm transistors meet specifications in the International Technology Roadmap for Semiconductors (ITRS) roadmap.

http://www.physorg.com/news123.html

 

[karlotta]

so what are they saying? UMC does have non Low~k at 90nm. TSMC made a 130nm Low~k. So it doesnt have to be FSG if 130nm. TSMC 110nm is FSG.

 

[Razor1]

so what are they saying? UMC does have non Low~k at 90nm. TSMC made a 130nm Low~k. So it doesnt have to be FSG if 130nm. TSMC 110nm is FSG.

Oops I meant no they don't have only low-k .09

 

[KimB]

So, ahem, will NVidia ever release 90nm desktop parts, or will it start at 80nm?

Well, I believe the GeForce 6150 is a 90nm desktop part

In all seriousness, though, I expect we'll see at least a couple 90nm desktop GPU's within the next couple of months (such as the rumored G71).

 

[Fodder]

In all seriousness, though, I expect we'll see at least a couple 90nm desktop GPU's within the next couple of months (such as the rumored G71).

Or this one.

 

[Robbitop]

actually are there any process smaller then .11 without some kind of insulation?

IMO that isn't exactly correct. Between any wiring layer needs to be a dielectricum. For example 130nm- and 110nm High Performance processes were using "FSG" as a dielectricum. But the lowk means that the "k value" of the dielectricum is under 3. As a result the inductive resistance drops. And lower induction + resistance results in higher possible clock rates because the flanks are less crippled.

sry for my bad english

 

[Razor1]

IMO that isn't exactly correct. Between any wiring layer needs to be a dielectricum. For example 130nm- and 110nm High Performance processes were using "FSG" as a dielectricum. But the lowk means that the "k value" of the dielectricum is under 3. As a result the inductive resistance drops. And lower induction + resistance results in higher possible clock rates because the flanks are less crippled.

sry for my bad english

Yeah you're right overlooked FSG as an insulator , thinking its pretty much used in most silicon chip processes hehe.