TSMC 90nm production schedules

Asicnewbie: Actually, I'm not 100% sure it's a per-working-chip basis. It's maybe that TSMC pays 50% of the costs for non-working chips or something, don't remember clearly, and not sure those details are even public - and I also remember they claimed to be the only TSMC partner in such a position. I'll have to google this...

Also, one of the primary reasons TSMC accepted that deal is that nVidia helps them for new processes. That's right. Being pretty much one of the most aggressive TSMC partner ( and they learnt their lesson this time I hope ) , they probably provided a testing ground for TSMC - big ASICs on new processes. Just guessing that, but I'm sure the official reason is that they helps them for new technology ( that might be through giving them cash for things like Low-K, though... )

And what is nVidia doing? Well, they're paying IBM to develop two well known technologies, *and* they are paying for privileges ( I guess that probably means priority for their wafers )


Uttar
 
Also, one of the primary reasons TSMC accepted that deal is that nVidia helps them for new processes. That's right.

Everyone does. ATI had issues with R100 that they assisted TSMC in ironing out the 180nm process, and that benefitted NV15.
 
I question exactly how much R&D TSMC and UMC put forth in developing a new process. They're supplied by companies like Applied Materials with all of their equipment.
 
asicnewbie: Samsung is to Korea as IBM is to the world. They have the most advanced fabs and offer ASIC services, but everything is strictly on their terms at their prices, and schedules may change at any time according to the whims of Samsung's biggest customer: themselves.

RussShultz: Sure, fabs buy their components like we buy computer parts; everything from polished wafers to standard cell libraries. Even Intel, for example, buys their lithography tools from Nikon or AMSL. But a 130 nm fab does not work out-of-the-box and setting one up is not for the faint-of-heart. An extreme case of shopping for fabs is a Korean foundry that recently bought an entire functioning 180 nm fab from a Japanese foundry. A year and a half after the move and with external help, the line is finally qualified.
 
[url=http://siliconstrategies.com/article/showArticle.jhtml;jsessionid=1152WGGIL1B3SQSNDBCSKHSCJUMEIJVN?articleId=13000149 said:
Silicon Strategies[/url]]"Nvidia has informed its add-in board partners that yield problems on the NV35 and NV31 will be remedied by the end of August," McConnell wrote in a report issued today.

The problems with the NV31 and NV35 do not reside at TSMC. McConnell today told Silicon Strategies that the yield issues were "Nvidia-specific."
 
DaveBaumann said:
[url=http://siliconstrategies.com/article/showArticle.jhtml;jsessionid=1152WGGIL1B3SQSNDBCSKHSCJUMEIJVN?articleId=13000149 said:
Silicon Strategies[/url]]"Nvidia has informed its add-in board partners that yield problems on the NV35 and NV31 will be remedied by the end of August," McConnell wrote in a report issued today.

The problems with the NV31 and NV35 do not reside at TSMC. McConnell today told Silicon Strategies that the yield issues were "Nvidia-specific."

Could that be because they are coming out with NV36 and NV38? lol

just spewing shizzle outta my mouth (err, fingers) so ignore me :)
 
Odd.
This is a forum that thrives on intelligent speculation, but nobody so far has speculated on products that will be introduced on 0.09um, in what market segments, when, by whom, under what conditions they will be pushed to market, and how this will impact 0.13um products available at the time.

Retrospective speculation is well and good, but the truly juicy stuff is ahead, not behind. :) The density benefits offered by 0.09um are too significant to be ignored.

Entropy
 
Given that low-k 130nm products aren't around yet I think the general consensus is that the next round of chips will be using that process, and then its likely thay R500 and NV50 will move to 90nm.
 
DaveBaumann said:
Given that low-k 130nm products aren't around yet I think the general consensus is that the next round of chips will be using that process, and then its likely thay R500 and NV50 will move to 90nm.

To illustrate what I'm talking about, the relevant question for these parts is probably "when?". Assume, for speculations sake, that nVidias NV40 is lackluster in comparison to ATIs next generation part. Wouldn't they push ahead on the process front? What would that imply regarding the market longevity for the next generation high-end parts?

It has proven difficult to achieve low cost+low power+high performance for DX9 parts on the 0.13um node. The RV350 is arguably the most successful effort to date, but even that part offers fairly little over its predecessors on non-DX9 codes in spite of process advantages. When will someone try to leverage 0.09um in the mainstream? And why? Leaving low cost out of the equation allows us to speculate freely on gfx chips for mobile use, using process variations that keep leakage under control. Could moving rapidly to 0.09um help nVidia assault ATIs dominance in this segment? While density is probably the most significant advantage offered initially by 0.09um, power consumption at a given level of performance might be another reason for early adoption.

It would seem that the gfx-chip market will remain at 0.13um for all introductions made this year. But such a situation is not stable when the leading foundry is offering 0.09um volume production. After all, nVidia is TSMCs largest customer and ATI is not small fry either. It is difficult to envision that last 0.13um generation leading a long and comfortable life under such circumstances.

Entropy
 
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