Transistor count on 130nm process

[P4-Fan]

Does anyone know the largest practical size(transistor count) for graphic chips using the 130nm and 90nm process techs? Is Nvidia already pushing the limit size wise with their NV35 for 130nm?

It seems graphics chips have been growing faster than new lithography advances. Will graphics development be forced to slow down due to process technology/cost of the chips?

Thanks

 

[KimB]

Process technologies alone are slowing down. This slowdown will become much more dramatic in the next two to five years (to put it simply, Moore's law cannot continue for more than five years...it will have to slow down before that time, as current silicon-based technology just will not work below that size: new technology is needed).

Anyway, the actual numbers depend on a huge number of factors: exact process (there are many small variations at the same "size"), type of transistors (there are different densities for logic and SRAM, for example), and process maturity.

In the end, it's impossible to predict, but you can be sure that nVidia's current NV30 and NV35 are right at the upper end of what current .13 micron processes can produce. Maturity of the .13 micron process will allow for larger chips to be produced in volume (note that some foundries are further along than others).

 

[arjan de lumens]

There is no hard limit on the number of transistors possible to have per chip at any given process node - AFAIK, the largest 0.13 micron FPGAs available today have something like 200-300 million transistors' worth of logic, but at that size manufacturing costs are something like several thousand dollars per working chip (large chips -> few chips per wafer and low yield -> high costs). Such pricing is usually not a problem for the people that use FPGAs, but I doubt Nvidia is going to find many buyers to a $5000 GPU...

 

[overclocked]

Do you mean something like Itanium/2 etz (?)

 

[arjan de lumens]

Not really - FPGAs are quite different beasts from CPUs and GPUs - look here for a description of what an FPGA is.

I mentioned them because they are usually the first really large circuits to be mass-produced on new processes at TSMC/UMC-like foundries and often much larger than e.g. GPUs.

In the case of Itanium-series processors, most of the transistors are huge cache SRAMs, where it is rather easy to get good yields and reasonable prices (set aside 1-2% of the SRAM lines as a reserve and enable them if other lines are defective.)

 

[PC-Engine]

Anyone know how to convert gates to transistors?

 

[arjan de lumens]

The normal rule for ASICs: 1 gate = about 4 transistors. May vary depending on what you define as a 'gate', but the 4-transistor metric is the one most commonly used.

 

[PC-Engine]

The normal rule for ASICs: 1 gate = about 4 transistors. May vary depending on what you define as a 'gate', but the 4-transistor metric is the one most commonly used.

Cool thanks arjan de lumens

Ok so to answer the question asked in the orginal thread, using 4 transistors per gate as reference, you're looking at over 400 million transistors for a 0.09u process.

http://www.necel.com/en/process/ux6.html

 

[overclocked]

Thx for the link, if we relate this to Nv and ATI right now does .11nm come as a oasis if it´s viable that is. I have hard to se it viable now because the Low-k on 130nm is problematic and other tricks need to be solved before we can move up to 200milj+trans.

 

[Josiah]

AFAIK both R420 and NV40 are @ 130nm with around 150 million transistors, with R5xx and NV5x @ 90nm (right?)