Jawed
Legend
Xenos uses a "pipeline temp":
http://www.beyond3d.com/forum/showthread.php?p=689500&highlight=adds_prev#post689500
seemingly as a way to get around register bandwidth limitations.
(Note on my posting: vec3+scalar+SF isn't possible, I wasn't thinking straight, sigh.)
And judging from:
Method and Apparatus for Multi-thread Accumulation Buffering in a Computation Engine
variants of this kind of technique are widely used in ATI's GPUs (I haven't actually read this patent, or other patent documents for stuff that's very similar - just judging from the diagrams).
That dates from 2000, and it prolly explains the "less than expected" VS performance that raises comments from time to time. Guessing...
Jawed
http://www.beyond3d.com/forum/showthread.php?p=689500&highlight=adds_prev#post689500
seemingly as a way to get around register bandwidth limitations.
(Note on my posting: vec3+scalar+SF isn't possible, I wasn't thinking straight, sigh.)
And judging from:
Method and Apparatus for Multi-thread Accumulation Buffering in a Computation Engine
variants of this kind of technique are widely used in ATI's GPUs (I haven't actually read this patent, or other patent documents for stuff that's very similar - just judging from the diagrams).
That dates from 2000, and it prolly explains the "less than expected" VS performance that raises comments from time to time. Guessing...
Jawed