Sandy Bridge socket exposed to public view!

[Grall]

http://www.xtremesystems.org/forums/showthread.php?t=256851

Some random data I picked up:
2011-pin (leaf?) land-grid array
TWO securing levers - one at each end of the socket
4-channel DDR3 memory controller
40 lanes of PCIe 3.0!

Monster chip... I wonder how AMD can compete against this. Of course, so much badass tech is sure to be expensive, so there'll surely be plenty space at mainstream and budget sectors of the market to fight over.

 

[itsmydamnation]

16 core bulldozer/12core magny cours has quad channel memory, its 1974 pins(G34) with 42 PCI-e lanes(from the NB), so i fail to see how new socket == "badass tech" or how AMD are going to struggle to keep up with the new Mhz race (pin count).

granted its PCI-e2 v 3 but there isn't a whole lot of things that will need that kind of bandwidth in a hurry, CNA's/HBA's and thats about it really. From what i have seen AMD's next chipset isn't due until the first "refresh" of the bulldozer design.

 

[Grall]

AMDs current CPUs can't digest even the bandwidth available from their current dual channel memory interfaces, much less quad channel, due to internal bottlenecks. This hasn't been fixed in magny cours, which is shown by benchmarks...

As for struggle to keep up - when was the last time AMD released a core that could compete in raw performance with Intel's offerings? It's not happened since the bad old Pentium4 days, half a decade ago or more.

Of course, there's a "slight" difference in the research and development resources available at both companies... AMD just doesn't have the same kind of muscle in those departments - basically nobody else does. So it's understandable if they're getting trounced performance-wise, it pretty much can't be avoided unless Intel screws itself up again like they did with the P4.

 

[fehu]

maybe amd can hope in another i820

bulldozer will be new and even llano will have a new memory controller, wait hope and see