r520 to feature unified shaders?
- Thread starter BruteForce170
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geo said:Was I the only one who had their mouse hovering over their rep button here?The ps saved him. . .this time.
Ahhh man, I could have used the positive rep.
I guess I need to be more cut throat to survive on B3D Anyhow...
We did a REALLY good job of killing this thread. Nice job guys. Its nice to know we can all pull together and kill a lame rumor when needed!
We either kill it or we immortalize it. Right, 32-pipe R520?
hoom
Veteran
Well if it has the ring bus system like r500 but with seperate vertex & pixel shaders, as per mostly Jawed (which I thoroughly agree with at least on principle that they wouldn't/shouldn't take this long to make just effectively an overclocked, die shrink r420 with fp32 even if there is not really any solid evidence for it), then a not entirely clued up person might mistake that for 'unified shaders'.
I'd be inclined to call the ring bus a 'unified architecture' in that it divides & links up the functional components in a logical manner with equal access from one component to the next, but it doesn't necessarily imply 'unified shaders', they are an optional extra level of unification.
I'd be inclined to call the ring bus a 'unified architecture' in that it divides & links up the functional components in a logical manner with equal access from one component to the next, but it doesn't necessarily imply 'unified shaders', they are an optional extra level of unification.
Okay, we all understand I'm bouncing on my technical toes here to keep my nose above water, right? (I can see Baumann's next post, "Glub! Glub!") With that out of the way. . .
Look at Huddy's answer re whether we'd see Xenos two-die e-dram solution in the pc space. What he said was, roughly, "It is so complex and expensive that it don't scale worth a damn down the family". Yet we're going to see, if reports are to be believed, a ring bus (1/2 width) on RV530.
I certainly expect (said it enuf, so no surprise there!) to see some similarity here and there between Xenos pieces and R520 pieces, but I don't see any conflict between that idea and Wavey's pounding into us that Xenos answers at a macro level will not be R520 (or even R600) answers at a macro level.
A little more concretely, mightn't it be the case that once they decided to go with the separate die and e-dram for Xenos, that very decision might have made the ring bus both 1) less useful and 2) less attractive from a performance perspective for use in Xenos specifically, rather than less attractive and less useful for transitioning your way to a unified architecture in the pc space that doesn't have the separate die and e-dram?
(I can see Baumann's next post, "Glub! Glub!") With that out of the way. . .Look at Huddy's answer re whether we'd see Xenos two-die e-dram solution in the pc space. What he said was, roughly, "It is so complex and expensive that it don't scale worth a damn down the family". Yet we're going to see, if reports are to be believed, a ring bus (1/2 width) on RV530.
I certainly expect (said it enuf, so no surprise there!) to see some similarity here and there between Xenos pieces and R520 pieces, but I don't see any conflict between that idea and Wavey's pounding into us that Xenos answers at a macro level will not be R520 (or even R600) answers at a macro level.
A little more concretely, mightn't it be the case that once they decided to go with the separate die and e-dram for Xenos, that very decision might have made the ring bus both 1) less useful and 2) less attractive from a performance perspective for use in Xenos specifically, rather than less attractive and less useful for transitioning your way to a unified architecture in the pc space that doesn't have the separate die and e-dram?
Jawed
Legend
I think it's possible to argue that EDRAM and the ring bus are sort of mutually exclusive - the interface to EDRAM is independent of the interface to GDDR3 RAM, so why even contemplate sharing the datapaths?
Whereas in a conventional GPU GDDR3 is doing everything.
But I honestly wouldn't argue it very strongly. I dare say that's because one way or another, anything to be learned from such a discussion doesn't appear to be very interesting. It's on a par with a discussion of R580 potentially having a 512-bit bus. It's a nice thing to speculate on, and the impacts are somewhat obvious. But it's a rather short and only mildly diverting road.
Still, here I am
(And, to be fair, such a discussion could impart new ideas about the function of a ring bus. So I'm only half dismissive...)
I suppose I prefer to see the ring bus as a feature left out of Xenos in order for the design team to focus on getting it out the door - focussing on the absolute must-haves, unified shader architecture, MEMEXPORT, tessellation, de-coupled texture pipes, EDRAM and not to forget, XPS.
R520/515/530 represent a different mix of risks, and take cognisance of the fact that a USA is somewhat hamstrung/out-of-place if it's not the full DX10 pipeline (now there's an interesting discussion - it aint necessarily true...) - so ATI can risk a bit of "ring bus" and an "out of order batch-scheduler" with "fully decoupled texture pipes".
In fact, it's good practice to experiment with architectural components like this before bringing the whole shooting match together in one component, i.e. R600.
Sounds convincing, doesn't it
Jawed
Whereas in a conventional GPU GDDR3 is doing everything.
But I honestly wouldn't argue it very strongly. I dare say that's because one way or another, anything to be learned from such a discussion doesn't appear to be very interesting. It's on a par with a discussion of R580 potentially having a 512-bit bus. It's a nice thing to speculate on, and the impacts are somewhat obvious. But it's a rather short and only mildly diverting road.
Still, here I am
(And, to be fair, such a discussion could impart new ideas about the function of a ring bus. So I'm only half dismissive...)I suppose I prefer to see the ring bus as a feature left out of Xenos in order for the design team to focus on getting it out the door - focussing on the absolute must-haves, unified shader architecture, MEMEXPORT, tessellation, de-coupled texture pipes, EDRAM and not to forget, XPS.
R520/515/530 represent a different mix of risks, and take cognisance of the fact that a USA is somewhat hamstrung/out-of-place if it's not the full DX10 pipeline (now there's an interesting discussion - it aint necessarily true...) - so ATI can risk a bit of "ring bus" and an "out of order batch-scheduler" with "fully decoupled texture pipes".
In fact, it's good practice to experiment with architectural components like this before bringing the whole shooting match together in one component, i.e. R600.
Sounds convincing, doesn't it
Jawed
geo said:
There is another aspect of the Xenos eDRAM solution that makes it very hard for ATI to incorporate it into other GPU's of theirs.
Microsoft owns the patent for the "smart" eDRAM, not ATI. ATI could possibly go with "dumb" eDRAM, which would be nothing more than a frame buffer, but if they wanted to add in the extra logic for FSAA and such, they would have to pay MS royalties.
Jawed said:
Your phrase, not mine.
Tho of course I can't say you're wrong either, and I'll still count this one more right than wrong if your analysis on this scenario prevails. I'm talking about scalability and usefullness, rather than a bright-line test. On scalability I've already pointed at Huddy and RV530. On usefullness, I'd note that Xenos has a pretty narrow range of output scenarios to hit (compared to pc), which must have some decided impact on the predictability of where the bottlenecks will appear in the large picture of the various elements as well; and if you ain't a bottleneck, why "spend" on it?Edit: By whatever analysis, my bottom line is I'm not willing to come to conclusions about the utility of a ring bus to a unified architecture just because it isn't on Xenos and is on an (apparently not fully unified) R520.
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Hellbinder
Banned
radeonic2 said:Nice one HB.
But.. after all these years on forums you still don't check your spelling/typos
Hey, i was in a hurry this morning.
/me hands Ailuros a piece of chalk
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