R500 to have more than 200 million transistors?

[MuFu]

Loci can't be at the DFT, it's far too late for that.

Not that I've been following the 'where's loci now' discussions, but DFT (which I'm assuming is scan insertion) comes at the end, right before initial tapeout.

They add the test structures right before tapeout? Isn't that a bit tricky with the layout being finalised? The phrase "DFT" seems to suggest it's something that is considered from the very earliest stages.

I am way out of my depth here, lol.

MuFu.

 

[RussSchultz]

I'm sure the added size is accounted for in the top level layout, but it doesn't need to be there to do sims, etc so its usually the last thing that gets worked on. Then its iterating autoroute/fix critical path until its up to speed.

 

[T2k]

BTW, I still believe there's no way on earth to get 90 nano ready by the next year.

I do.
Depends on exactly what "by next year" is supposed to mean.

I mean product - manufactured on 90 nanometer - will be shipped.

Next year is long. Most fabs are quite far come with their 90nm processess if press-releases are to be believed.

Most fabs can't even utilize the required 130 nano process by this year.
Talk about original R400...

Quite a few roadmaps would have to be scrapped if 90nm didn't start producing until 2005.

I have little doubt that there will be 90nm product shipped during 2004, by all the usual suspects.

Entropy

I doubt it. Really. Maximum some mainstream or light chip as "tryout", like RV350.

 

[Arun]

Yeah, 2004 sounds too utopic for serious 0.09
Although a product announcement at Comdex and avaibility in very early 2005 might be possible. Maybe the NV45 will be that. Just speculating here.


Uttar

 

[KnightBreed]

Are any of the major fabs offering intermediate processes, like 110nm?

nVidia has gone from 250 -> 220 -> 180 -> 150 -> 130nm. What would lead you to believe either ATi or nVidia would jump directly to 90nm?

 

[megadrive0088]

sorry, what is 'Loci' ??? ive seen it mentioned in numerous threads. is that the code name for the re-done R400 (the R420) or R390?

also, 200M transistors seems like it would be for a R4XX chip. if they are to nearly double the complexity of R300/R350 - 200M would be it. ATI has been roughly doubling complexity (and pipelines) since R100/Radeon64.
200M seems too little for a monster like R500. the R500 should be at least in the 350M+ range, or more, along with NV50, in 2005.

then again, maybe it is R500. but that doesnt really make much sense to me. they are talking about an upcoming ATI chip right? so why jump to R500, a likely 2005 release now, when we haven't seen R4XX VPUs yet.

 

[MuFu]

sorry, what is 'Loci' ??? ive seen it mentioned in numerous threads. is that the code name for the re-done R400 (the R420) or R390?

When the original R400 was delayed and then eventually canned, ATi drafted specs for a new part that would be based on the R300 but take performance to levels that would have been expected from the abandoned, next-gen part. This project was given the name "Loci", but those who initally worked on it didn't like that codename and used "R390" instead. Although this is technically the most appropriate name for the ASIC, it doesn't look too good from a marketing point of view so the powers that be tried changed it to "R400". That proved so confusing that soon they had to change the "official" project name once more to R420. I'm not quite sure what the situation is currently - I suspect we'll come to know of it as "R400", but it is still referred to internally by a variety of names, AFAIK.

So Loci is R390, R400 and R420, it's just most convenient to use the fancy name for speculatory purposes, IMHO. The original R400 evolved into what is now R500.

MuFu.

 

[demalion]

With the Cadence talk, it just seems that the most likely reality for Loci is a one chip execution of "MAXX" (goes with the name Loci, AND that favorite ATI rumor workhorse ).

I'm-a-thinking that elimination of redundancy that doesn't require replication per pipeline (vertex and pixel) would fit pretty well with 200 million, and that with the Cadence rumor it would be pretty much a matter of getting a working 4fragment/2vertex pipe setup (i.e., like already exisits in the RV350), but including all the R350 features, on 0.13, and then replicating that while only having to newly hand tune the adapted intra-pipe circuitry.
Given that intra-pipe circuitry might actually have to grow more than double for dealing with more than 8 pipes, and that the vertex processing performance of the R350 is already pretty hefty for the near future, maybe that replication part (vertex pipelines) will be skimped on a bit.

Oh, [/over the top speculation]

A ridiculously clocked 0.13 but-slightly-beefed R350 would work too, but that's pretty "boring" speculation.

 

[MuFu]

I don't think it'll be that complicated - 8x2 and clocked very fast, with some small steps towards PS/VS 3.0 compliancy and perhaps an evolution of their HOS engine that can handle early PP requirements.

MuFu.

 

[Joe DeFuria]

I don't think it'll be that complicated - 8x2 and clocked very fast, with some small steps towards PS/VS 3.0 compliancy and perhaps an evolution of their HOS engine that can handle early PP requirements.

I think that's a reasonable guess. We have to keep in mind that any fill-rate increases should be met with reasonable bandwidth increases. (Otherwise, from the IHV perspective, you are wasting money.)

So something like a dual-core (MAXX) only really makes sense if it's paired with double the bandwidth: a 512 bit DDR bus. I don't expect raw memory bandiwdth this fall or early next spring to be anything but an evolutionary step over today's top cards. 500-600 Mhz DDR ram on a 256 bit bus.

An 600 Mhz or so 8x2 core, however, while still likely being bandwidth limited with such memory, though far from ideal, isn't a gross mis-match. It would be in fact a more balanced architecture than the 9500 Pro.

 

[MuFu]

I agree that it's far from ideal but seems balanced considering a modest advance in memory tech (~>2nd gen GDDR2). What has lead me to believe this is the most likely spec is the fact that I was told it will probably be faster than the original R400 would have been overall, with the notable individual exception of stencil-based rendering. I imagine R400 would have been capable of a full 16 pixel/clock output in such situations (16x0, if you like) but not clocked as fast and the only other alternative would be an 8x1 design that would have to be clocked very, very fast indeed in order to meet performance targets (~700Mhz, I would guess).

I can almost hear the ATi employees browsing this thread chuckling to themselves.

MuFu.

 

[Joe DeFuria]

I agree that it's far from ideal but seems balanced considering a modest advance in memory tech (~>2nd gen GDDR2)

Right. It's no less balanced (assuming similarly clocked core and memory) than the GeForce3/4ti boards, which are 4x2 on a 128 bit DDR bus. It'll be memory bandwidth limited in many cases, but it's a decent performance increase from 4x1, while not being as expensive and wasteful as 8x1 on the same bus.

The only potential downside, is that Loci's pixel shading performance (barring any major chages from R350 pipes), will only increase as much as the clock rate. Luckily for ATI, shading performance of the R3x00 core is one of its strong points relative to the NV3x core.

I also hope, with the advent of 256 MB of memory, that they boost the AA sampling up to 8X, or even 10X.

 

[demalion]

Durnit, can't I sprinkle "MAXX" around and propose over the top speculation in peace?



Hmm, your stencil commentary does sort of work against it, but barring that, I don't really want to underestimate the board design capabilities of ATI. They do have multiple R300 cores on a card, correct? Wouldn't that indicate some 256 bit x 2 design effort already? However, chip packaging expense isn't reflected by that.

Maybe I'm just being unrealistic regarding them, though...why I thought it was reasonable is because I recall a comment about further bus width increase from ATI regarding the R400 (atleast, that is my recollection of the association), and to achieve more performance than that, it would seem natural (and quite possible, if they were planning to anyways) that Loci be aimed in that direction as well.

Also, there is maybe the possibility a QDR type approach, but things have been pretty quiet on that front for a while, haven't they? I had actually thought that, originally, the end of the year was the target for such RAM technology.

Throw a hurdle in my path, and my speculation goes "over the top" of it...

 

[Saem]

Durnit, can't I sprinkle "MAXX" around and propose over the top speculation in peace?

I think ATI keeps MAXX development around as a just in case. If anyone seriously beats the pants off their top of the line, they can release a MAXX to at least not LOOK like they're getting owned.

We'll see a MAXX if and when somebody releases a card which hammers the products of the time.

 

[megadrive0088]

So Loci includes R390, R400 and R420 and it is not clear what the exact situation is with all of these VPUs. ok understandable. things are kinda murky

where as the R400 and R500 used to be pretty clear, in terms of generation and team designing it, it is now up in the air somewhat....

guess we'll find out.

 

[MuFu]

So Loci includes R390, R400 and R420 and it is not clear what the exact situation is with all of these VPUs.

Hmm... not really. It's just one ASIC that is being refered to by all these names (with the exception of "R400", which is still used for the current R500 sometimes, lol).

MuFu.

Edit - sp

 

[RussSchultz]

Hahha. We do that too: change the product codename/designation halfway through. Its so fun combing through the datasheets and code to remove all vestiges of the previous codename/designation; changing all the email aliases from one to the other, and even correcting each other in discussions when some people just won't give up the original name.

 

[Typ55]

So which vs/ps version will loci probably get?

Isn't it too dangerous not to have vs3.0/ps3.0 while Nvidias NV40 project has?

 

[Arun]

Isn't it too dangerous not to have vs3.0/ps3.0 while Nvidias NV40 project has?

But isn't it even more dangerous to set too high a target and fail miserably?

*cough* NV30 *cough*


Uttar

 

[Unit01]

What's NV30?