R500 to have more than 200 million transistors?
- Thread starter MuFu
- Start date
3D tech is advancing at a monstrous rate. Are we to expect a 200M transistor, 130nm VPU to debut this winter or next spring? Spring would coincide nicely with ATi's self-imposed doubling performance every 18-months with a new architecture, but would that push R500 too far away? Is a 90nm R500 a feasible goal for next year at all?
I never thought I'd be bothered by too many new cards. Spring seems reasonable, but to expect three new high-end cards in one year (R350, 360, 390) seems a bit preposterous.
I never thought I'd be bothered by too many new cards. Spring seems reasonable, but to expect three new high-end cards in one year (R350, 360, 390) seems a bit preposterous.
Joe DeFuria
Legend
It's not all that clear to me if the 200 million transistor part referred to is Loci, or R500. I would tend to expect the latter...but you never know. 
As per the NV40 speculation saying 350 M transistors re http://www.beyond3d.com/forum/viewtopic.php?t=5669
That is alot of complex silicon, lets wait and see! Without a die shrink or two that's alot of gates to power - how much juice would that many transistors need at high frequency? You might need quite a big PSU just for your 3d card.
That is alot of complex silicon, lets wait and see! Without a die shrink or two that's alot of gates to power - how much juice would that many transistors need at high frequency? You might need quite a big PSU just for your 3d card.
WOW !
200 Mio Transistors _only_ for logic. So with an logic/SRAM-mix like in the Ti4600, this "Beast" will very likely have nearly 300Mio Transistors.
So ATi will do it again, designing an highend chip with very high transistor count on an outdated-process. Nvidia needs 90nm for the next chip and ATi has an chip with nearly the same complexity ("judged" from the rumours) on 130nm. Hopefully they can strike again, as with the R300 last year.
200 Mio Transistors _only_ for logic. So with an logic/SRAM-mix like in the Ti4600, this "Beast" will very likely have nearly 300Mio Transistors.
So ATi will do it again, designing an highend chip with very high transistor count on an outdated-process. Nvidia needs 90nm for the next chip and ATi has an chip with nearly the same complexity ("judged" from the rumours) on 130nm. Hopefully they can strike again, as with the R300 last year.
Lezmaka said:
Someone could say that R300/R350 is already dual cored. Two cores that share some things and don't share others. For example the frontend seems 'shared' (up to rasterization) and the backend (pixel pipes) seems separated as they work as two 2x2 pixel blocks.
In any case, unless there is a need for 'multithreading 3D' I don't see a point to real multicore on a chip GPUs comparable with the CPU CMPs.
DegustatoR
Legend
R500 presumably will be 0,09. R400 - 0,13. But I doubt that R400 will have 300mil transistors...mboeller said:
NV40 will be 0,13. Dunno about NV45. And NV50 will presumably be 0,09. But it's a Spring-Summer 2005 product.
Just my thoughts, though.
Lezmaka said:
IBM is allready making dual core processors and has done so for some time.
http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power4.html#chip
Tim said:
without even getting into the Cell discussion....
asicnewbie
Newcomer
Nice catch, MuFu! I did a search on 'Nvidia' at www.synopsys.com, and it turned up some interesting stuff.
According to this (http://www.synopsys.com/corporate/exec_presentation/2002/jexec2002_tokyo_sanjiv.pdf) Synopsys powerpoint presentation, the NV25 engineering design-flow centered around Synopsys's tools. (Admittedly, I can't tell whether Synopsys omitted competitor's tools from their presentation. And there is no proof that every named Synopsys tools was the primary contributor at a milestone.)
As for ATI, a Cadence press-release (http://www.cadence.com/company/pr/012003_ATI.html)indicates ATI picked Cadence's SOCEncounter suite over the Synopsys 'equivalent', if there is one. (Synopsys GalaxyDesign suite is an approximate equivalent. A designer could mix/match individual tools from either suites, at his own risk.)
The fun part (for me anyway), is seeing the parallels between ATI/NVidia marketing and the EDA-tool vendor marketing. Like any other industry where big $$$ are involved, EDA-tool vendors play high-stakes marketing games. I.e., tool-vendors want to be able to identify satisfied customers when marketing their expensive CAD packages. Their PR-department is always delighted to get client permission to release tape-out info, for a particular CAD-product.
In the past, both Cadence and Synopsys (competitors) would issue press-releases celebrating XX #tapeouts enabled by their EDA-tools. There was a huge stink on what exactly constitued a 'real tapeout.' Did the tape-out go into production? (A few 'tape-outs' never reached the fab, which sort of contradicts the traditional definition of 'tape-out.') Did the first silicon match the tool's predicted (modeled) results? And finally, did the customer's design-team actually *use* the tool, or did the vendor's application engineers do all the real work?
According to this (http://www.synopsys.com/corporate/exec_presentation/2002/jexec2002_tokyo_sanjiv.pdf) Synopsys powerpoint presentation, the NV25 engineering design-flow centered around Synopsys's tools. (Admittedly, I can't tell whether Synopsys omitted competitor's tools from their presentation. And there is no proof that every named Synopsys tools was the primary contributor at a milestone.)
As for ATI, a Cadence press-release (http://www.cadence.com/company/pr/012003_ATI.html)indicates ATI picked Cadence's SOCEncounter suite over the Synopsys 'equivalent', if there is one. (Synopsys GalaxyDesign suite is an approximate equivalent. A designer could mix/match individual tools from either suites, at his own risk.)
The fun part (for me anyway), is seeing the parallels between ATI/NVidia marketing and the EDA-tool vendor marketing. Like any other industry where big $$$ are involved, EDA-tool vendors play high-stakes marketing games. I.e., tool-vendors want to be able to identify satisfied customers when marketing their expensive CAD packages. Their PR-department is always delighted to get client permission to release tape-out info, for a particular CAD-product.
In the past, both Cadence and Synopsys (competitors) would issue press-releases celebrating XX #tapeouts enabled by their EDA-tools. There was a huge stink on what exactly constitued a 'real tapeout.' Did the tape-out go into production? (A few 'tape-outs' never reached the fab, which sort of contradicts the traditional definition of 'tape-out.') Did the first silicon match the tool's predicted (modeled) results? And finally, did the customer's design-team actually *use* the tool, or did the vendor's application engineers do all the real work?
T2k said:
I do.
Depends on exactly what "by next year" is supposed to mean. Next year is long. Most fabs are quite far come with their 90nm processess if press-releases are to be believed. Quite a few roadmaps would have to be scrapped if 90nm didn't start producing until 2005.
I have little doubt that there will be 90nm product shipped during 2004, by all the usual suspects.
Entropy
MuFu said:
Not that I've been following the 'where's loci now' discussions, but DFT (which I'm assuming is scan insertion) comes at the end, right before initial tapeout.