Quaz51 said:http://www.toshiba.co.jp/about/press/2004_06/pr1601.htm
Thanks for the heads-up Quaz51.
From the Toshiba PR annoucement
In addition to the elemental technologies announced today, Toshiba is working with Sony group on 45-nanometer process technologies for next generation system LSI, including embedded memory technology.
New technologies
1) MOSFET (metal-oxide semiconductor field-effect transistor):
Improved device performance and lower power consumption requires reduction of the power supply voltage. Such an approach requires a thinner film of oxide, which is more prone to current leakage. This has proved to be a major issue.
Toshiba's new MOSFET has an ultra-thin gate oxide film. The EOT (equivalent oxide thickness) is less than 1nm thick and 1.5-order reduction in current leakage is realized from conventional SiON film. The new film was achieved by optimizing the oxide film process technology, and it solves the problem of performance deterioration due to increased leakage current with a thinner oxide film. The MOSFET achieves superior characteristics: a drive current of 820uA/um has been obtained for an NMOSET, and of 300uA/um for a PMOSFET at 0.85V (Ioff=50nA/um).
2) Multi Layer Wiring:
Toshiba has found the optimized wiring parameters in terms of operating frequency and power consumption for 45 nm generation system LSI. The new technology demonstrates a 130nm pitch of the first metal layer, a 72% shrink from the 65nm generation.
So, the people who said that STI were originaly aiming to 45nm when designing their Cell CPU (BE), even if the firsts samples were made with the 65nm tech, were maybe right...