Not really a case most of the time probably, due to the horrifically low efficiency of said RDRAM interface... I believe ERP said they did some measurements of RAM latency on the N64 and concluded it was around 250ns or something ludicrous like that, I can't quite recall the exact numbers stated so I may be off.
Actually quite a bit worse:
http://forum.beyond3d.com/showpost.php?p=394753&postcount=17
Uncertain what the costs are like for a cache miss, or if this is what he was referring to. I've seen some CPUs were uncached reads actually performed more poorly than cache misses.
However, much of this is likely due to the interface between the CPU and the chip that has the RSP and RDP (RCP), the latter of which has the memory controller. Hopefully the RDP and DMA controller didn't have as severe problems due to memory latency problems..
9th bit was hardware parity used by the RDRAM interface I believe. It would probably lead to some very odd alignment issues if it accessed the DRAM array directly...
9th bit was directly accessible to at least the RDP. I don't think there was a way for the CPU to see it (maybe it used it for parity itself or maybe the memory controller handled that optionally), but the RDP could read and write it, and therefore there were effectively 18bpp framebuffer formats. You could get 3-bits of coverage in addition to 15-bits of color, for instance.
IIRC it's worse than that, bilinear filter ran at half-rate and trilinear at quarter rate I believe.
Yeah so with filtering off, which it almost never was in games (but neither was depth buffering). I wonder if it ran at lower rate with depth buffering too. Bandwidth was cited as the culprit but if it needed more clocks for it..