IBM claims new eDRAM will double processor performance

[JNewt427]

Posted 2/14/07 from Tom's Hardware. Very Interesting !

http://www.tgdaily.com/2007/02/14/ibm_edram/

And Welcome to all, as this is my first post here.

 

[Heinrich4]

Posted 2/14/07 from Tom's Hardware. Very Interesting !

http://www.tgdaily.com/2007/02/14/ibm_edram/

And Welcome to all, as this is my first post here.

Thanx for link/information and welcome!

And i'm remenber 4/5 years ago infos about patents Cell BE and Vizualizer and eDRAM (if not me deceit 64MB eDRAM).

 

[Shifty Geezer]

Key excerpt :

Shown as a 65 nm concept at the currently held International Solid State Circuits Conference (ISSCC), IBM claims that the eDRAM exceeds the performance of conventional SRAM, which is typically used for on-die CPU cache, in about one-third the space with one-fifth the standby power.

This gen, might it find it's way onto XB360 for a considerable cost saving? And going forwards, this could be a valuable replacement for SRAM in the Cell's LSs, allowing perhaps 512 KB per core in less space for more SPEs per die.

 

[3dilettante]

The latency numbers being given out make it look like it's only faster if used as an L3 cache.
SRAM latencies are still lower for the faster levels of cache.

 

[TheChefO]

Posted 2/14/07 from Tom's Hardware. Very Interesting !

http://www.tgdaily.com/2007/02/14/ibm_edram/

And Welcome to all, as this is my first post here.

Thanks for the link and welcome to B3D! :smile:

The latency numbers being given out make it look like it's only faster if used as an L3 cache.
SRAM latencies are still lower for the faster levels of cache.

Thanks for the insight. So how does this tech compare to typical edram designs?

 

[Blazkowicz]

how does it compare to AMD's ZRAM, too?

 

[nonamer]

I think this is ZRAM, or a variant of it.

 

[nonamer]

Speaking of which, my prediction here: http://www.beyond3d.com/forum/showpost.php?p=892179&postcount=5

sounds more plausible now. I pretty much expect massive eDRAM caches/scratchpads to be the normal in the next generation.

 

[Capeta]

eDRAM is already being used as a texture cache in GC, nothing new here.

 

[Megadrive1988]

eDRAM has been in use for almost a decade.

1.) the 3D0 MX, which was basicly M2.5. was the first consumer device designed with embedded video memory. MX almost became the graphics for Nintendo's N2000, before being ditched for Dolphin/GCN, which supposedly borrowed some elements of MX.

2.) unreleased Verite V4400e 3D accelerator circa 1999

3.) PS2 Graphics Synthesizer designed in the mid to late 90s, coming onto the market in March 2000.


I very much hope PS4 uses huge amounts of embedded memory in its GPU/CGPU/GPGPU and its CPU.

 

[Platon]

So could this be use in xenos 2 then and in sufficient amount to avoid tilling?...

 

[Capeta]

So could this be use in xenos 2 then and in sufficient amount to avoid tilling?...

I don't understand your question. Xenos already uses eDRAM so there's nothing preventing Xenos2 from using more of the same eDRAM. This is nothing new. It's hype over nothing. The only thing that's different here is IBM is using SOI for this eDRAM instead of the standard bulk process. Normally it's very difficult to have bulk process eDRAM and SOI logic in a single die eg it's usually bulk process eDRAM+bulk proces logic like what you currently have in Xenos. This SOI eDRAM could be used with chips like CELL which is fabbed using SOI instead of bulk process.

 

[Acert93]

So could this be use in xenos 2 then and in sufficient amount to avoid tilling?...

It really depends on when the Xbox 3 is released and what the targer resolution is. At the rate silicon continues to advance we could see eDRAM 8x larger if the time the Xbox 3 launches in the 2010-2012 timeframe. A 1080p framebuffer with 4xMSAA and using a 32bit color depth format and 32bit Z/stencile buffer would need about 64MB to avoid tiling. For FP16 your would need about 128MB. If price and future process node drops become uncertain I would think 64MB would be likely. 1080p/FP10/4xMSAA and 1080p/FP16/2xMSAA, and with tiling still on the table you could go higher if you wanted in terms of MSAA, color format, or resolution. Maybe some better tiling logic could also be designed.

It seems plausible that Sony and MS could use eDRAM and utilize it as a framebuffer. But I would also wonder if they could possibly go with a more flexible design that allowed the eDRAM to be more versatile as well.

 

[Capeta]

I honestly don't see the size of eDRAM being a huge issue going forward because you could always mount more eDRAM dies onto the same package as a SiP. For example the Hollywood GPU at 90nm already has 24MB of eDRAM in a separate die and if needed you could just add another 24MB eDRAM die onto the same SiP. This means you can have 48MB of eDRAM at 90nm. At 45nm you could have close to 100MB of eDRAM. Cost would be the limiting factor AFAICS.

 

[StefanS]

I honestly don't see the size of eDRAM being a huge issue going forward because you could always mount more eDRAM dies onto the same package as a SiP. For example the Hollywood GPU at 90nm already has 24MB of eDRAM in a separate die and if needed you could just add another 24MB eDRAM die onto the same SiP. This means you can have 48MB of eDRAM at 90nm. At 45nm you could have close to 100MB of eDRAM. Cost would be the limiting factor AFAICS.

Ehm those 24 MB are not eDRAM.

 

[Capeta]

Ehm those 24 MB are not eDRAM.

Then what is it?

 

[Platon]

I don't understand your question. Xenos already uses eDRAM so there's nothing preventing Xenos2 from using more of the same eDRAM. This is nothing new. It's hype over nothing. The only thing that's different here is IBM is using SOI for this eDRAM instead of the standard bulk process. Normally it's very difficult to have bulk process eDRAM and SOI logic in a single die eg it's usually bulk process eDRAM+bulk proces logic like what you currently have in Xenos. This SOI eDRAM could be used with chips like CELL which is fabbed using SOI instead of bulk process.

Just thought it was some new form of EDRAM, that is smaller and cheaper and thus you could have more of it for less $ so I though that future designs of xenos would go the route of much more edram to avoid tilling but still not cost an arm and a leg. Didn't now that this was the god ol edram made differently, didn't read the link provided ...

 

[StefanS]

Then what is it?

Just a normal external 24MB 1T-SRAM chip, just like in GCN.

 

[Platon]

It really depends on when the Xbox 3 is released and what the targer resolution is. At the rate silicon continues to advance we could see eDRAM 8x larger if the time the Xbox 3 launches in the 2010-2012 timeframe. A 1080p framebuffer with 4xMSAA and using a 32bit color depth format and 32bit Z/stencile buffer would need about 64MB to avoid tiling. For FP16 your would need about 128MB. If price and future process node drops become uncertain I would think 64MB would be likely. 1080p/FP10/4xMSAA and 1080p/FP16/2xMSAA, and with tiling still on the table you could go higher if you wanted in terms of MSAA, color format, or resolution. Maybe some better tiling logic could also be designed.

It seems plausible that Sony and MS could use eDRAM and utilize it as a framebuffer. But I would also wonder if they could possibly go with a more flexible design that allowed the eDRAM to be more versatile as well.

I always thought that the next gen xenos would go fr 64MB of edram, it would just seems like a reasonable jump forward. I guess whether they use edram all together is in question as well and I guess that depends a lot on how they will handle backwards compatitbility next time, if they care about it or not...

 

[Capeta]

Just a normal external 24MB 1T-SRAM chip, just like in GCN.

It doesn't look like an external 1T-SRAM chip to me. It looks exactly like what you see in Xenos. If the die is close to 132mm^2 then it's eDRAM.

Edit: Ok it doesn't look like it could be eDRAM since the die turns out to be 95mm^2.