The_Wolf_Who_Cried_Boy
Newcomer
Why do designers stick with using only bilinear capable TMU's.
IIRC the GF3 (or 4?) had TMU's capable of single cycle trilinear filtering, so such a thing is possble.
I would guess the interconnect routing and control logic would be easier to implement for 16 trilinear TMU's rather than 32 bilinear units, which as chips become more complex and mutithreading capable would have to be a consideration.
From my limited grasp of what happend under the hood, generally speaking a TMU would spend most of it's life performing anisotropic filtering on anything up to 128 samples, so why continue to focus it's design on bilinear? Is the relative cost to the transistor budget that great? Am I missing something?
IIRC the GF3 (or 4?) had TMU's capable of single cycle trilinear filtering, so such a thing is possble.
I would guess the interconnect routing and control logic would be easier to implement for 16 trilinear TMU's rather than 32 bilinear units, which as chips become more complex and mutithreading capable would have to be a consideration.
From my limited grasp of what happend under the hood, generally speaking a TMU would spend most of it's life performing anisotropic filtering on anything up to 128 samples, so why continue to focus it's design on bilinear? Is the relative cost to the transistor budget that great? Am I missing something?
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