Does anyone know why Nvidia opted for a 128-bit bus instead of a 256-bit one? I've always assumed it was b/c they ran out of transistors and had to decide between having CineFX features (128bit fp, massively programmable shaders, etc.) or having a 256-bit bus. Instead, they created a 128-bit bus with nearly the performance of a 256-bit one, using DDR2. Is that right, or were there other more significant reasons why they chose not to use a 256-bit bus? How many extra transistors would the 256-bit bus require?
GFFX: How many more transistors would 256-bit bus require?
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arjan de lumens
Veteran
Not so sure that this applies for a given amount of bandwidth - if we compare GFFX (128-bit) and R9700 (256-bit) reference PCB layouts, the GFFX board is substantially larger and has more layers (IIRC, 12 vs 8 ), despite supporting at least 20% less memory bandwidth.Tahir said:
arjan de lumens
Veteran
As for the transistor count with a 256-bit bus: The additional raw DRAM controllers don't take up very many additional transistors (~1-2 million, if not less). However, in order to benefit from the 256-bit bus, many datapaths and buffers all over the chip have to be widened. Also, certain units, such as the frame/Z compression units, have to be widened as well to keep them from becoming bottlenecks in the design. These factors can add substantially to the size of the design - although exactly how much is really anybody's best guess.
I personally think that NVIDIA did not use 256bit because at the time of design NVIDIA may have thought a 256bit was not feasible on a mass scale. Parhelia showed this was not correct and so did R300 but by that time (or at the time the 256bit implementation idea feasability assessment) may have been too late for NVIDIA to do a redesign.
My own take is that they thought that for a 4x2 (or 4 whatever they want to call it now) architecture a 128 bit bus was good enough, as it had been good enough for NV2X and R2XX. And I think that it makes sense. However R300 arrived being 8x1 and using a 256 bit bus so NVidia had to overclock the NV30 which made them had problems with the memory (the more GPU clock speed more the bandwidth needed) and had to use that 500 MHz DDR2 memory to keep the pace.
Hi everybody!
First post from a longtime reader.
I remember that last year, after the launch of Parhelia, David Kirk was asked about Parhelias 256 bit memory bus and if and when nvidia would move to it. His answer was, that such a bus would only make sense if you double the pipelines at the same time, for a 4 pipe design it would be overkill and that they would move to it when it becomes necessary.
I always thought that was a pretty reasonable statement and was surprised when nvidia announced the GFFX as an 8 pipe 128 bit design. So my answer to the original posters question is, they didn't implement a 256 bit memory bus for nv30, because, as it is a 4 pipe design, it doesn't need one.
Since the nv35 seems to have the 256 bit memory bus, I think it is pretty safe to assume it will be able to write 8 pixels per clock.
First post from a longtime reader.
I remember that last year, after the launch of Parhelia, David Kirk was asked about Parhelias 256 bit memory bus and if and when nvidia would move to it. His answer was, that such a bus would only make sense if you double the pipelines at the same time, for a 4 pipe design it would be overkill and that they would move to it when it becomes necessary.
I always thought that was a pretty reasonable statement and was surprised when nvidia announced the GFFX as an 8 pipe 128 bit design. So my answer to the original posters question is, they didn't implement a 256 bit memory bus for nv30, because, as it is a 4 pipe design, it doesn't need one.
Since the nv35 seems to have the 256 bit memory bus, I think it is pretty safe to assume it will be able to write 8 pixels per clock.
megadrive0088
Regular
he is saying that Nvidia's next highend chip, NV35, will use a 256-bit bus and be a true 8 pixel pipeline GPU.
the NV30 (GeForceFX) is a 4 pipeline chip with a 128-bit bus.
the NV30 (GeForceFX) is a 4 pipeline chip with a 128-bit bus.
Well, Kirk said in the interview I mentioned in my other post, that for a 4 pipe design a 128 bit memory bus would be sufficient, but in order to truely benefit from a 256 bit bus, you'll need 8 pipes. This was at the time of the Parhelia launch, when he was asked about the benefits of its 256 bit bus and if nvidia was considering something similar in the future.
I think it was mufu who mentioned in another thread nv35 will use a 256 bit memory bus. That's why I speculated that nv35 will be a true 8 pipe design, because it would perfectly fit Kirks reasoning in that old interview.
I think it was mufu who mentioned in another thread nv35 will use a 256 bit memory bus. That's why I speculated that nv35 will be a true 8 pipe design, because it would perfectly fit Kirks reasoning in that old interview.
Taking the NV3X design from 4 pipe 128 bit memory to 8 pipe 256 bit memory is a fairly major redsign from my understaning. Now I'm not saying saying Mufu's wrong (if that is what he said) but I remain to be convinced as I don't think Nvidia need such a major redesign for a refresh.
Switching to a 256 bit may only add a few mil trans tot he design but from 4 to 8 pipes would really blow the budget.
Switching to a 256 bit may only add a few mil trans tot he design but from 4 to 8 pipes would really blow the budget.
Heathen said:
I think what is generally accepted is that th nv30 already has 8 pipelines, but only 4 of them have the ability to output colored pixels. enabling the rest of them to do this may or may not add very many transistors. maybe not even as much as adding the 256bit bus.
Really, where? I don't think I've seen a shred of evidence to actually suggest this yet. Everything NVIDIA has talked about to developers actually stated that it worked as a 2x2 pipeline configuration, as NVIDIA have since GTS.
Sure, some may accept that there are multiple shader execution units 'per-pipe' but that doesn't make it have '8 pipelines'. The other problem is that its shader performance hasn't done much to persuade us here yet.
Its a 2x2 pipeline configuration - i.e. it has four pipelines arranged to operate in a 2x2 square.
With 8 texture units NV30 is still relatively bandwidth constrained even under normal operating conditions, let alone with AA. ATI didn't go for single cycle trilinear even with a 256bit bus because of insufficient bandwidth, so there are gains to be made even with the same pipeline config.
With 8 texture units NV30 is still relatively bandwidth constrained even under normal operating conditions, let alone with AA. ATI didn't go for single cycle trilinear even with a 256bit bus because of insufficient bandwidth, so there are gains to be made even with the same pipeline config.
Why smaller? Would that be down to some in core optimisations?
Well, it seems as though with the NV31 they avoided some of the architectural "issues" of the NV30; if the NV31 is more representative of what the NV35 will be then the NV30 is, it's easy to see how the NV35 could be smaller and yet faster than the NV30.
I think the NV30 has been kind of a bad dream for NVidia.
I think the NV30 has been kind of a bad dream for NVidia.
